https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/177334
>From db343bced75941388377314b78eabe0f5c5501c1 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 8 Jan 2026 16:08:36 +0000 Subject: [PATCH 1/2] [AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe For FEAT_FPRCVT instructions, allow them to run in streaming mode if safe --- .../Target/AArch64/AArch64ISelLowering.cpp | 3 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +- .../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 126 +++++------------- .../CodeGen/AArch64/arm64-cvtf-simd-itofp.ll | 30 ++--- 4 files changed, 49 insertions(+), 114 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index eabea8ffb10e4..f1170e7100290 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -20542,6 +20542,9 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG, N->getOpcode() == ISD::FP_TO_UINT_SAT) return SDValue(); + if (Subtarget->isStreaming() && Subtarget->hasFPRCVT()) + return SDValue(); + if (!Subtarget->isSVEorStreamingSVEAvailable() || (!Subtarget->isStreaming() && !Subtarget->isStreamingCompatible())) return SDValue(); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 212c3891e1387..0bad2fe0e8d6b 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -5330,7 +5330,7 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>; defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; -let Predicates = [HasNEON, HasFPRCVT] in{ +let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in{ defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas", int_aarch64_neon_fcvtas>; defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau", int_aarch64_neon_fcvtau>; defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms", int_aarch64_neon_fcvtms>; @@ -5373,7 +5373,7 @@ def : Pat<(i64 (any_llround f64:$Rn)), defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>; defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>; -let Predicates = [HasNEON, HasFPRCVT] in { +let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in { defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf", any_sint_to_fp>; defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf", any_uint_to_fp>; diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll index 7dd0806758d28..7f05aefda4dc2 100644 --- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll +++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll @@ -36,8 +36,7 @@ define float @test_fptosi_f16_i32_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptosi_f16_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzs s0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd: @@ -66,8 +65,7 @@ define double @test_fptosi_f16_i64_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptosi_f16_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzs d0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd: @@ -122,8 +120,7 @@ define double @test_fptosi_f32_i64_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptosi_f32_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd: @@ -151,8 +148,7 @@ define double @test_fptosi_f64_i64_simd(double %a) { ; ; CHECK-SME-LABEL: test_fptosi_f64_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd: @@ -181,8 +177,7 @@ define float @test_fptosi_f32_i32_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptosi_f32_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd: @@ -211,8 +206,7 @@ define float @test_fptoui_f16_i32_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptoui_f16_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzu s0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd: @@ -241,8 +235,7 @@ define double @test_fptoui_f16_i64_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptoui_f16_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzu d0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd: @@ -297,8 +290,7 @@ define double @test_fptoui_f32_i64_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptoui_f32_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd: @@ -326,8 +318,7 @@ define double @test_fptoui_f64_i64_simd(double %a) { ; ; CHECK-SME-LABEL: test_fptoui_f64_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzu d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd: @@ -356,8 +347,7 @@ define float @test_fptoui_f32_i32_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptoui_f32_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzu s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd: @@ -706,9 +696,7 @@ define double @fcvtas_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtas_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtas d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtas_ds_round_simd: @@ -764,9 +752,7 @@ define float @fcvtas_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtas_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtas s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtas_ss_round_simd: @@ -795,9 +781,7 @@ define double @fcvtas_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtas_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtas d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtas_dd_round_simd: @@ -828,9 +812,7 @@ define double @fcvtau_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtau_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtau d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtau_ds_round_simd: @@ -886,9 +868,7 @@ define float @fcvtau_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtau_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtas s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtau_ss_round_simd: @@ -917,9 +897,7 @@ define double @fcvtau_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtau_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtas d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtau_dd_round_simd: @@ -1192,9 +1170,7 @@ define double @fcvtms_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtms_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtms d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtms_ds_round_simd: @@ -1250,9 +1226,7 @@ define float @fcvtms_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtms_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtms s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtms_ss_round_simd: @@ -1281,9 +1255,7 @@ define double @fcvtms_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtms_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtms d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtms_dd_round_simd: @@ -1315,9 +1287,7 @@ define double @fcvtmu_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtmu_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtmu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtmu_ds_round_simd: @@ -1373,9 +1343,7 @@ define float @fcvtmu_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtmu_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtms s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtmu_ss_round_simd: @@ -1404,9 +1372,7 @@ define double @fcvtmu_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtmu_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtms d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtmu_dd_round_simd: @@ -1437,9 +1403,7 @@ define double @fcvtps_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtps_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtps d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtps_ds_round_simd: @@ -1495,9 +1459,7 @@ define float @fcvtps_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtps_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtps s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtps_ss_round_simd: @@ -1526,9 +1488,7 @@ define double @fcvtps_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtps_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtps d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtps_dd_round_simd: @@ -1559,9 +1519,7 @@ define double @fcvtpu_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtpu_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtpu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtpu_ds_round_simd: @@ -1617,9 +1575,7 @@ define float @fcvtpu_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtpu_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtps s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtpu_ss_round_simd: @@ -1648,9 +1604,7 @@ define double @fcvtpu_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtpu_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtps d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtpu_dd_round_simd: @@ -1681,9 +1635,7 @@ define double @fcvtzs_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzs_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_ds_round_simd: @@ -1739,9 +1691,7 @@ define float @fcvtzs_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzs_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_ss_round_simd: @@ -1770,9 +1720,7 @@ define double @fcvtzs_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtzs_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_dd_round_simd: @@ -1802,9 +1750,7 @@ define double @fcvtzu_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzu_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_ds_round_simd: @@ -1860,9 +1806,7 @@ define float @fcvtzu_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzu_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_ss_round_simd: @@ -1891,9 +1835,7 @@ define double @fcvtzu_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtzu_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_dd_round_simd: diff --git a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll index ab7d880b0d8e6..44594fad93d08 100644 --- a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll +++ b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll @@ -51,8 +51,7 @@ define half @scvtf_bitcast_f32_to_f16(float %f) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.s +; CHECK-SME-NEXT: scvtf h0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f16: @@ -75,8 +74,7 @@ define half @ucvtf_bitcast_f32_to_f16(float %f) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.s +; CHECK-SME-NEXT: ucvtf h0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f16: @@ -99,8 +97,7 @@ define float @scvtf_bitcast_f64_to_f32(double %d) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.d +; CHECK-SME-NEXT: scvtf s0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f32: @@ -123,8 +120,7 @@ define float @ucvtf_bitcast_f64_to_f32(double %d) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.d +; CHECK-SME-NEXT: ucvtf s0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f32: @@ -147,8 +143,7 @@ define half @scvtf_bitcast_f64_to_f16(double %d) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.d +; CHECK-SME-NEXT: scvtf h0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f16: @@ -171,8 +166,7 @@ define half @ucvtf_bitcast_f64_to_f16(double %d) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.d +; CHECK-SME-NEXT: ucvtf h0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f16: @@ -195,8 +189,7 @@ define float @scvtf_bitcast_f32_to_f32(float %f) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.s +; CHECK-SME-NEXT: scvtf s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f32: @@ -219,8 +212,7 @@ define float @ucvtf_bitcast_f32_to_f32(float %f) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.s +; CHECK-SME-NEXT: ucvtf s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f32: @@ -243,8 +235,7 @@ define double @scvtf_bitcast_f64_to_f64(double %d) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f64: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: scvtf z0.d, p0/m, z0.d +; CHECK-SME-NEXT: scvtf d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f64: @@ -267,8 +258,7 @@ define double @ucvtf_bitcast_f64_to_f64(double %d) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f64: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: ucvtf z0.d, p0/m, z0.d +; CHECK-SME-NEXT: ucvtf d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f64: >From 7315c2aac3da3447618124250718946f3cc600dd Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Mon, 2 Feb 2026 14:01:24 +0000 Subject: [PATCH 2/2] fixup! [AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe Remove tryToReplaceScalarFPConversionWithSVE() function and use only [HasFPRCVT] --- .../Target/AArch64/AArch64ISelLowering.cpp | 64 ---- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +- .../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 224 +++--------- .../CodeGen/AArch64/arm64-cvtf-simd-itofp.ll | 50 +-- .../sve-streaming-mode-cvt-fp-int-fp.ll | 30 +- .../sve-streaming-mode-cvt-fp-to-int.ll | 40 +- .../sve-streaming-mode-cvt-int-to-fp.ll | 40 +- ...e-streaming-mode-fixed-length-fp-to-int.ll | 346 ++++++++++-------- ...e-streaming-mode-fixed-length-int-to-fp.ll | 94 ++--- 9 files changed, 318 insertions(+), 574 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index f1170e7100290..3ee632b4e8d6b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -20526,62 +20526,6 @@ static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N, return SDValue(); } -/// Tries to replace scalar FP <-> INT conversions with SVE in streaming -/// functions, this can help to reduce the number of fmovs to/from GPRs. -static SDValue -tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const AArch64Subtarget *Subtarget) { - if (N->isStrictFPOpcode()) - return SDValue(); - - if (DCI.isBeforeLegalizeOps()) - return SDValue(); - - if (N->getOpcode() == ISD::FP_TO_SINT_SAT || - N->getOpcode() == ISD::FP_TO_UINT_SAT) - return SDValue(); - - if (Subtarget->isStreaming() && Subtarget->hasFPRCVT()) - return SDValue(); - - if (!Subtarget->isSVEorStreamingSVEAvailable() || - (!Subtarget->isStreaming() && !Subtarget->isStreamingCompatible())) - return SDValue(); - - auto isSupportedType = [](EVT VT) { - return !VT.isVector() && VT != MVT::bf16 && VT != MVT::f128; - }; - - SDValue SrcVal = N->getOperand(0); - EVT SrcTy = SrcVal.getValueType(); - EVT DestTy = N->getValueType(0); - - if (!isSupportedType(SrcTy) || !isSupportedType(DestTy)) - return SDValue(); - - EVT SrcVecTy; - EVT DestVecTy; - if (DestTy.bitsGT(SrcTy)) { - DestVecTy = getPackedSVEVectorVT(DestTy); - SrcVecTy = DestVecTy.changeVectorElementType(*DAG.getContext(), SrcTy); - } else { - SrcVecTy = getPackedSVEVectorVT(SrcTy); - DestVecTy = SrcVecTy.changeVectorElementType(*DAG.getContext(), DestTy); - } - - // Ensure the resulting src/dest vector type is legal. - if (SrcVecTy == MVT::nxv2i32 || DestVecTy == MVT::nxv2i32) - return SDValue(); - - SDLoc DL(N); - SDValue ZeroIdx = DAG.getVectorIdxConstant(0, DL); - SDValue Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, SrcVecTy, - DAG.getPOISON(SrcVecTy), SrcVal, ZeroIdx); - SDValue Convert = DAG.getNode(N->getOpcode(), DL, DestVecTy, Vec); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestTy, Convert, ZeroIdx); -} - static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) { @@ -20590,10 +20534,6 @@ static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG, if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG)) return Res; - if (SDValue Res = - tryToReplaceScalarFPConversionWithSVE(N, DAG, DCI, Subtarget)) - return Res; - EVT VT = N->getValueType(0); if (VT != MVT::f16 && VT != MVT::f32 && VT != MVT::f64) return SDValue(); @@ -20634,10 +20574,6 @@ static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG, static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) { - if (SDValue Res = - tryToReplaceScalarFPConversionWithSVE(N, DAG, DCI, Subtarget)) - return Res; - if (!Subtarget->isNeonAvailable()) return SDValue(); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 0bad2fe0e8d6b..c1a8768fe5266 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -5330,7 +5330,7 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>; defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; -let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in{ +let Predicates = [HasFPRCVT] in{ defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas", int_aarch64_neon_fcvtas>; defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau", int_aarch64_neon_fcvtau>; defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms", int_aarch64_neon_fcvtms>; @@ -5373,7 +5373,7 @@ def : Pat<(i64 (any_llround f64:$Rn)), defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>; defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>; -let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in { +let Predicates = [HasFPRCVT] in { defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf", any_sint_to_fp>; defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf", any_uint_to_fp>; diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll index 7f05aefda4dc2..7b6cd56dadaaa 100644 --- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll +++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll @@ -41,10 +41,7 @@ define float @test_fptosi_f16_i32_simd(half %a) { ; ; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.h -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs s0, h0 ; CHECK-SVE-NEXT: ret %r = fptosi half %a to i32 %bc = bitcast i32 %r to float @@ -70,10 +67,7 @@ define double @test_fptosi_f16_i64_simd(half %a) { ; ; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.h -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, h0 ; CHECK-SVE-NEXT: ret %r = fptosi half %a to i64 %bc = bitcast i64 %r to double @@ -125,10 +119,7 @@ define double @test_fptosi_f32_i64_simd(float %a) { ; ; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, s0 ; CHECK-SVE-NEXT: ret %r = fptosi float %a to i64 %bc = bitcast i64 %r to double @@ -153,10 +144,7 @@ define double @test_fptosi_f64_i64_simd(double %a) { ; ; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, d0 ; CHECK-SVE-NEXT: ret %r = fptosi double %a to i64 %bc = bitcast i64 %r to double @@ -182,10 +170,7 @@ define float @test_fptosi_f32_i32_simd(float %a) { ; ; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs s0, s0 ; CHECK-SVE-NEXT: ret %r = fptosi float %a to i32 %bc = bitcast i32 %r to float @@ -211,10 +196,7 @@ define float @test_fptoui_f16_i32_simd(half %a) { ; ; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.h -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzu s0, h0 ; CHECK-SVE-NEXT: ret %r = fptoui half %a to i32 %bc = bitcast i32 %r to float @@ -240,10 +222,7 @@ define double @test_fptoui_f16_i64_simd(half %a) { ; ; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.h -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzu d0, h0 ; CHECK-SVE-NEXT: ret %r = fptoui half %a to i64 %bc = bitcast i64 %r to double @@ -295,10 +274,7 @@ define double @test_fptoui_f32_i64_simd(float %a) { ; ; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzu d0, s0 ; CHECK-SVE-NEXT: ret %r = fptoui float %a to i64 %bc = bitcast i64 %r to double @@ -323,10 +299,7 @@ define double @test_fptoui_f64_i64_simd(double %a) { ; ; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzu d0, d0 ; CHECK-SVE-NEXT: ret %r = fptoui double %a to i64 %bc = bitcast i64 %r to double @@ -352,10 +325,7 @@ define float @test_fptoui_f32_i32_simd(float %a) { ; ; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzu s0, s0 ; CHECK-SVE-NEXT: ret %r = fptoui float %a to i32 %bc = bitcast i32 %r to float @@ -701,10 +671,7 @@ define double @fcvtas_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtas_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frinta s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtas d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.round.f32(float %a) %i = fptosi float %r to i64 @@ -757,10 +724,7 @@ define float @fcvtas_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtas_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frinta s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtas s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.round.f32(float %a) %i = fptosi float %r to i32 @@ -786,10 +750,7 @@ define double @fcvtas_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtas_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frinta d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtas d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.round.f64(double %a) %i = fptosi double %r to i64 @@ -817,10 +778,7 @@ define double @fcvtau_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtau_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frinta s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtau d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.round.f32(float %a) %i = fptoui float %r to i64 @@ -873,10 +831,7 @@ define float @fcvtau_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtau_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frinta s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtas s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.round.f32(float %a) %i = fptosi float %r to i32 @@ -902,10 +857,7 @@ define double @fcvtau_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtau_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frinta d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtas d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.round.f64(double %a) %i = fptosi double %r to i64 @@ -927,17 +879,12 @@ define double @fcvtns_ds_roundeven_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtns_ds_roundeven_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintn s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtns d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtns_ds_roundeven_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintn s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtns d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.roundeven.f32(float %a) %i = fptosi float %r to i64 @@ -985,17 +932,12 @@ define float @fcvtns_ss_roundeven_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtns_ss_roundeven_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintn s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtns s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtns_ss_roundeven_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintn s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtns s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.roundeven.f32(float %a) %i = fptosi float %r to i32 @@ -1016,17 +958,12 @@ define double @fcvtns_dd_roundeven_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtns_dd_roundeven_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintn d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtns d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtns_dd_roundeven_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintn d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtns d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.roundeven.f64(double %a) %i = fptosi double %r to i64 @@ -1049,17 +986,12 @@ define double @fcvtnu_ds_roundeven_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtnu_ds_roundeven_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintn s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtnu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtnu_ds_roundeven_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintn s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtnu d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.roundeven.f32(float %a) %i = fptoui float %r to i64 @@ -1107,17 +1039,12 @@ define float @fcvtnu_ss_roundeven_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtnu_ss_roundeven_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintn s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtnu s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtnu_ss_roundeven_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintn s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtnu s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.roundeven.f32(float %a) %i = fptoui float %r to i32 @@ -1138,17 +1065,12 @@ define double @fcvtnu_dd_roundeven_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtnu_dd_roundeven_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintn d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtnu d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtnu_dd_roundeven_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintn d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtnu d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.roundeven.f64(double %a) %i = fptoui double %r to i64 @@ -1175,10 +1097,7 @@ define double @fcvtms_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtms_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintm s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtms d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.floor.f32(float %a) %i = fptosi float %r to i64 @@ -1231,10 +1150,7 @@ define float @fcvtms_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtms_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintm s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtms s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.floor.f32(float %a) %i = fptosi float %r to i32 @@ -1260,10 +1176,7 @@ define double @fcvtms_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtms_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintm d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtms d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.floor.f64(double %a) %i = fptosi double %r to i64 @@ -1292,10 +1205,7 @@ define double @fcvtmu_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtmu_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintm s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtmu d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.floor.f32(float %a) %i = fptoui float %r to i64 @@ -1348,10 +1258,7 @@ define float @fcvtmu_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtmu_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintm s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtms s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.floor.f32(float %a) %i = fptosi float %r to i32 @@ -1377,10 +1284,7 @@ define double @fcvtmu_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtmu_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintm d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtms d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.floor.f64(double %a) %i = fptosi double %r to i64 @@ -1408,10 +1312,7 @@ define double @fcvtps_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtps_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintp s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtps d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.ceil.f32(float %a) %i = fptosi float %r to i64 @@ -1464,10 +1365,7 @@ define float @fcvtps_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtps_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintp s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtps s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.ceil.f32(float %a) %i = fptosi float %r to i32 @@ -1493,10 +1391,7 @@ define double @fcvtps_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtps_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintp d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtps d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.ceil.f64(double %a) %i = fptosi double %r to i64 @@ -1524,10 +1419,7 @@ define double @fcvtpu_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtpu_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintp s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtpu d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.ceil.f32(float %a) %i = fptoui float %r to i64 @@ -1580,10 +1472,7 @@ define float @fcvtpu_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtpu_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintp s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtps s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.ceil.f32(float %a) %i = fptosi float %r to i32 @@ -1609,10 +1498,7 @@ define double @fcvtpu_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtpu_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintp d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtps d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.ceil.f64(double %a) %i = fptosi double %r to i64 @@ -1640,10 +1526,7 @@ define double @fcvtzs_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtzs_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintz s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.trunc.f32(float %a) %i = fptosi float %r to i64 @@ -1696,10 +1579,7 @@ define float @fcvtzs_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtzs_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintz s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.trunc.f32(float %a) %i = fptosi float %r to i32 @@ -1725,10 +1605,7 @@ define double @fcvtzs_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtzs_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintz d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.trunc.f64(double %a) %i = fptosi double %r to i64 @@ -1755,10 +1632,7 @@ define double @fcvtzu_ds_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtzu_ds_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintz s0, s0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzu d0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.trunc.f32(float %a) %i = fptoui float %r to i64 @@ -1811,10 +1685,7 @@ define float @fcvtzu_ss_round_simd(float %a) { ; ; CHECK-SVE-LABEL: fcvtzu_ss_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintz s0, s0 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs s0, s0 ; CHECK-SVE-NEXT: ret %r = call float @llvm.trunc.f32(float %a) %i = fptosi float %r to i32 @@ -1840,10 +1711,7 @@ define double @fcvtzu_dd_round_simd(double %a) { ; ; CHECK-SVE-LABEL: fcvtzu_dd_round_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: frintz d0, d0 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, d0 ; CHECK-SVE-NEXT: ret %r = call double @llvm.trunc.f64(double %a) %i = fptosi double %r to i64 diff --git a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll index 44594fad93d08..1d2bf1f6b9b7f 100644 --- a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll +++ b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll @@ -56,10 +56,7 @@ define half @scvtf_bitcast_f32_to_f16(float %f) nounwind { ; ; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f16: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: scvtf z0.h, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-SVE-NEXT: scvtf h0, s0 ; CHECK-SVE-NEXT: ret %i = bitcast float %f to i32 %r = sitofp i32 %i to half @@ -79,10 +76,7 @@ define half @ucvtf_bitcast_f32_to_f16(float %f) nounwind { ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f16: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: ucvtf z0.h, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-SVE-NEXT: ucvtf h0, s0 ; CHECK-SVE-NEXT: ret %i = bitcast float %f to i32 %r = uitofp i32 %i to half @@ -102,10 +96,7 @@ define float @scvtf_bitcast_f64_to_f32(double %d) nounwind { ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f32: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: scvtf z0.s, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: scvtf s0, d0 ; CHECK-SVE-NEXT: ret %i = bitcast double %d to i64 %r = sitofp i64 %i to float @@ -125,10 +116,7 @@ define float @ucvtf_bitcast_f64_to_f32(double %d) nounwind { ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f32: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: ucvtf z0.s, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: ucvtf s0, d0 ; CHECK-SVE-NEXT: ret %i = bitcast double %d to i64 %r = uitofp i64 %i to float @@ -148,10 +136,7 @@ define half @scvtf_bitcast_f64_to_f16(double %d) nounwind { ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f16: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: scvtf z0.h, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-SVE-NEXT: scvtf h0, d0 ; CHECK-SVE-NEXT: ret %i = bitcast double %d to i64 %r = sitofp i64 %i to half @@ -171,10 +156,7 @@ define half @ucvtf_bitcast_f64_to_f16(double %d) nounwind { ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f16: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: ucvtf z0.h, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-SVE-NEXT: ucvtf h0, d0 ; CHECK-SVE-NEXT: ret %i = bitcast double %d to i64 %r = uitofp i64 %i to half @@ -194,10 +176,7 @@ define float @scvtf_bitcast_f32_to_f32(float %f) nounwind { ; ; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f32: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: scvtf z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: scvtf s0, s0 ; CHECK-SVE-NEXT: ret %i = bitcast float %f to i32 %r = sitofp i32 %i to float @@ -217,10 +196,7 @@ define float @ucvtf_bitcast_f32_to_f32(float %f) nounwind { ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f32: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: ucvtf z0.s, p0/m, z0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: ucvtf s0, s0 ; CHECK-SVE-NEXT: ret %i = bitcast float %f to i32 %r = uitofp i32 %i to float @@ -240,10 +216,7 @@ define double @scvtf_bitcast_f64_to_f64(double %d) nounwind { ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f64: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: scvtf z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: scvtf d0, d0 ; CHECK-SVE-NEXT: ret %i = bitcast double %d to i64 %r = sitofp i64 %i to double @@ -263,10 +236,7 @@ define double @ucvtf_bitcast_f64_to_f64(double %d) nounwind { ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f64: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: ucvtf z0.d, p0/m, z0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: ucvtf d0, d0 ; CHECK-SVE-NEXT: ret %i = bitcast double %d to i64 %r = uitofp i64 %i to double diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll index 36b8220bb3338..2696a46801dfe 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll @@ -9,9 +9,8 @@ target triple = "aarch64-unknown-linux-gnu" define double @t1(double %x) { ; CHECK-LABEL: t1: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-NEXT: scvtf z0.d, p0/m, z0.d +; CHECK-NEXT: fcvtzs x8, d0 +; CHECK-NEXT: scvtf d0, x8 ; CHECK-NEXT: ret ; ; USE-NEON-NO-GPRS-LABEL: t1: @@ -34,9 +33,8 @@ entry: define float @t2(float %x) { ; CHECK-LABEL: t2: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-NEXT: scvtf z0.s, p0/m, z0.s +; CHECK-NEXT: fcvtzs w8, s0 +; CHECK-NEXT: scvtf s0, w8 ; CHECK-NEXT: ret ; ; USE-NEON-NO-GPRS-LABEL: t2: @@ -59,9 +57,8 @@ entry: define half @t3(half %x) { ; CHECK-LABEL: t3: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h -; CHECK-NEXT: scvtf z0.h, p0/m, z0.s +; CHECK-NEXT: fcvtzs w8, h0 +; CHECK-NEXT: scvtf h0, w8 ; CHECK-NEXT: ret ; ; USE-NEON-NO-GPRS-LABEL: t3: @@ -86,9 +83,8 @@ entry: define double @t4(double %x) { ; CHECK-LABEL: t4: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d -; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d +; CHECK-NEXT: fcvtzu x8, d0 +; CHECK-NEXT: ucvtf d0, x8 ; CHECK-NEXT: ret ; ; USE-NEON-NO-GPRS-LABEL: t4: @@ -111,9 +107,8 @@ entry: define float @t5(float %x) { ; CHECK-LABEL: t5: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s -; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s +; CHECK-NEXT: fcvtzu w8, s0 +; CHECK-NEXT: ucvtf s0, w8 ; CHECK-NEXT: ret ; ; USE-NEON-NO-GPRS-LABEL: t5: @@ -136,9 +131,8 @@ entry: define half @t6(half %x) { ; CHECK-LABEL: t6: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h -; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s +; CHECK-NEXT: fcvtzu w8, h0 +; CHECK-NEXT: ucvtf h0, w8 ; CHECK-NEXT: ret ; ; USE-NEON-NO-GPRS-LABEL: t6: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll index cfdc1baf8c282..6cf1132d9284c 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll @@ -8,9 +8,7 @@ target triple = "aarch64-unknown-linux-gnu" define i32 @f16_to_s32(half %x) { ; CHECK-LABEL: f16_to_s32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h -; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: fcvtzs w0, h0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f16_to_s32: @@ -26,9 +24,7 @@ define i32 @f16_to_s32(half %x) { define i64 @f16_to_s64(half %x) { ; CHECK-LABEL: f16_to_s64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h -; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: fcvtzs x0, h0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f16_to_s64: @@ -44,9 +40,7 @@ define i64 @f16_to_s64(half %x) { define i32 @f32_to_s32(float %x) { ; CHECK-LABEL: f32_to_s32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s -; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f32_to_s32: @@ -61,9 +55,7 @@ define i32 @f32_to_s32(float %x) { define i64 @f32_to_s64(float %x) { ; CHECK-LABEL: f32_to_s64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s -; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: fcvtzs x0, s0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f32_to_s64: @@ -93,9 +85,7 @@ define i32 @f64_to_s32(double %x) { define i64 @f64_to_s64(double %x) { ; CHECK-LABEL: f64_to_s64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d -; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: fcvtzs x0, d0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f64_to_s64: @@ -110,9 +100,7 @@ define i64 @f64_to_s64(double %x) { define i32 @f16_to_u32(half %x) { ; CHECK-LABEL: f16_to_u32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h -; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: fcvtzu w0, h0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f16_to_u32: @@ -128,9 +116,7 @@ define i32 @f16_to_u32(half %x) { define i64 @f16_to_u64(half %x) { ; CHECK-LABEL: f16_to_u64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h -; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: fcvtzu x0, h0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f16_to_u64: @@ -146,9 +132,7 @@ define i64 @f16_to_u64(half %x) { define i32 @f32_to_u32(float %x) { ; CHECK-LABEL: f32_to_u32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s -; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: fcvtzu w0, s0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f32_to_u32: @@ -163,9 +147,7 @@ define i32 @f32_to_u32(float %x) { define i64 @f32_to_u64(float %x) { ; CHECK-LABEL: f32_to_u64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s -; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: fcvtzu x0, s0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f32_to_u64: @@ -195,9 +177,7 @@ define i32 @f64_to_u32(double %x) { define i64 @f64_to_u64(double %x) { ; CHECK-LABEL: f64_to_u64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d -; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: fcvtzu x0, d0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: f64_to_u64: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll index 83403fc4ad86f..37e51f369e4bc 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll @@ -8,9 +8,7 @@ target triple = "aarch64-unknown-linux-gnu" define half @s32_to_f16(i32 %x) { ; CHECK-LABEL: s32_to_f16: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: scvtf z0.h, p0/m, z0.s +; CHECK-NEXT: scvtf h0, w0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: s32_to_f16: @@ -26,9 +24,7 @@ entry: define float @s32_to_f32(i32 %x) { ; CHECK-LABEL: s32_to_f32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: scvtf z0.s, p0/m, z0.s +; CHECK-NEXT: scvtf s0, w0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: s32_to_f32: @@ -58,9 +54,7 @@ entry: define half @u32_to_f16(i32 %x) { ; CHECK-LABEL: u32_to_f16: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s +; CHECK-NEXT: ucvtf h0, w0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: u32_to_f16: @@ -76,9 +70,7 @@ entry: define float @u32_to_f32(i32 %x) { ; CHECK-LABEL: u32_to_f32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s +; CHECK-NEXT: ucvtf s0, w0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: u32_to_f32: @@ -108,9 +100,7 @@ entry: define half @s64_to_f16(i64 %x) { ; CHECK-LABEL: s64_to_f16: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: scvtf z0.h, p0/m, z0.d +; CHECK-NEXT: scvtf h0, x0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: s64_to_f16: @@ -126,9 +116,7 @@ entry: define float @s64_to_f32(i64 %x) { ; CHECK-LABEL: s64_to_f32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: scvtf z0.s, p0/m, z0.d +; CHECK-NEXT: scvtf s0, x0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: s64_to_f32: @@ -143,9 +131,7 @@ entry: define double @s64_to_f64(i64 %x) { ; CHECK-LABEL: s64_to_f64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: scvtf z0.d, p0/m, z0.d +; CHECK-NEXT: scvtf d0, x0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: s64_to_f64: @@ -160,9 +146,7 @@ entry: define half @u64_to_f16(i64 %x) { ; CHECK-LABEL: u64_to_f16: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d +; CHECK-NEXT: ucvtf h0, x0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: u64_to_f16: @@ -178,9 +162,7 @@ entry: define float @u64_to_f32(i64 %x) { ; CHECK-LABEL: u64_to_f32: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d +; CHECK-NEXT: ucvtf s0, x0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: u64_to_f32: @@ -195,9 +177,7 @@ entry: define double @u64_to_f64(i64 %x) { ; CHECK-LABEL: u64_to_f64: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d +; CHECK-NEXT: ucvtf d0, x0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: u64_to_f64: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll index 76aa8e45ccda3..03736ad961612 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll @@ -421,10 +421,8 @@ define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) { define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) { ; CHECK-LABEL: fcvtzu_v1f16_v1i64: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: fcvtzu x8, h0 +; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzu_v1f16_v1i64: @@ -445,9 +443,10 @@ define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) { ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: mov z1.h, z0.h[1] -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h -; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h +; CHECK-NEXT: fcvtzu x8, h0 +; CHECK-NEXT: fcvtzu x9, h1 +; CHECK-NEXT: fmov d0, x8 +; CHECK-NEXT: fmov d1, x9 ; CHECK-NEXT: zip1 z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret @@ -475,17 +474,20 @@ define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) { ; CHECK-LABEL: fcvtzu_v4f16_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: mov z1.h, z0.h[3] ; CHECK-NEXT: mov z2.h, z0.h[2] ; CHECK-NEXT: mov z3.h, z0.h[1] -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h -; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h -; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.h -; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.h +; CHECK-NEXT: fcvtzu x10, h0 +; CHECK-NEXT: fcvtzu x8, h1 +; CHECK-NEXT: fcvtzu x9, h2 +; CHECK-NEXT: fcvtzu x11, h3 +; CHECK-NEXT: fmov d2, x10 +; CHECK-NEXT: fmov d0, x8 +; CHECK-NEXT: fmov d1, x9 +; CHECK-NEXT: zip1 z0.d, z1.d, z0.d +; CHECK-NEXT: fmov d1, x11 ; CHECK-NEXT: zip1 z1.d, z2.d, z1.d -; CHECK-NEXT: zip1 z0.d, z0.d, z3.d -; CHECK-NEXT: stp q0, q1, [x1] +; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i64: @@ -522,29 +524,36 @@ define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) { ; CHECK-LABEL: fcvtzu_v8f16_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: mov z2.h, z0.h[3] ; CHECK-NEXT: mov z3.h, z0.h[2] ; CHECK-NEXT: mov z4.h, z0.h[1] ; CHECK-NEXT: movprfx z1, z0 ; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8 -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h -; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.h -; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.h -; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.h +; CHECK-NEXT: fcvtzu x10, h0 +; CHECK-NEXT: fcvtzu x8, h2 +; CHECK-NEXT: fcvtzu x9, h3 +; CHECK-NEXT: fcvtzu x11, h4 ; CHECK-NEXT: mov z5.h, z1.h[3] ; CHECK-NEXT: mov z6.h, z1.h[2] -; CHECK-NEXT: mov z7.h, z1.h[1] -; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h -; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.h -; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.h -; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.h -; CHECK-NEXT: zip1 z2.d, z3.d, z2.d -; CHECK-NEXT: zip1 z0.d, z0.d, z4.d -; CHECK-NEXT: zip1 z3.d, z6.d, z5.d -; CHECK-NEXT: zip1 z1.d, z1.d, z7.d -; CHECK-NEXT: stp q0, q2, [x1] -; CHECK-NEXT: stp q1, q3, [x1, #32] +; CHECK-NEXT: mov z2.h, z1.h[1] +; CHECK-NEXT: fcvtzu x14, h1 +; CHECK-NEXT: fcvtzu x12, h5 +; CHECK-NEXT: fcvtzu x13, h6 +; CHECK-NEXT: fmov d0, x8 +; CHECK-NEXT: fmov d1, x9 +; CHECK-NEXT: fcvtzu x15, h2 +; CHECK-NEXT: fmov d2, x10 +; CHECK-NEXT: fmov d3, x11 +; CHECK-NEXT: zip1 z0.d, z1.d, z0.d +; CHECK-NEXT: fmov d1, x12 +; CHECK-NEXT: fmov d4, x13 +; CHECK-NEXT: zip1 z2.d, z2.d, z3.d +; CHECK-NEXT: fmov d3, x14 +; CHECK-NEXT: zip1 z1.d, z4.d, z1.d +; CHECK-NEXT: fmov d4, x15 +; CHECK-NEXT: stp q2, q0, [x1] +; CHECK-NEXT: zip1 z3.d, z3.d, z4.d +; CHECK-NEXT: stp q3, q1, [x1, #32] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i64: @@ -598,52 +607,66 @@ define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) { ; CHECK-LABEL: fcvtzu_v16f16_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mov z2.h, z1.h[1] -; CHECK-NEXT: mov z3.h, z0.h[3] -; CHECK-NEXT: mov z4.h, z0.h[2] -; CHECK-NEXT: movprfx z7, z1 -; CHECK-NEXT: fcvtzu z7.d, p0/m, z1.h -; CHECK-NEXT: movprfx z5, z1 -; CHECK-NEXT: ext z5.b, z5.b, z1.b, #8 -; CHECK-NEXT: movprfx z6, z0 -; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8 -; CHECK-NEXT: mov z16.h, z1.h[3] +; CHECK-NEXT: movprfx z2, z1 +; CHECK-NEXT: ext z2.b, z2.b, z1.b, #8 +; CHECK-NEXT: movprfx z4, z0 +; CHECK-NEXT: ext z4.b, z4.b, z0.b, #8 +; CHECK-NEXT: mov z3.h, z1.h[3] +; CHECK-NEXT: mov z5.h, z0.h[3] +; CHECK-NEXT: mov z6.h, z0.h[2] +; CHECK-NEXT: fcvtzu x8, h1 +; CHECK-NEXT: mov z7.h, z1.h[1] ; CHECK-NEXT: mov z1.h, z1.h[2] -; CHECK-NEXT: mov z17.h, z0.h[1] -; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.h -; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.h -; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.h -; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h -; CHECK-NEXT: mov z18.h, z5.h[3] -; CHECK-NEXT: mov z19.h, z6.h[3] -; CHECK-NEXT: mov z20.h, z6.h[2] -; CHECK-NEXT: fcvtzu z17.d, p0/m, z17.h -; CHECK-NEXT: mov z21.h, z6.h[1] -; CHECK-NEXT: fcvtzu z16.d, p0/m, z16.h -; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h -; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.h -; CHECK-NEXT: zip1 z2.d, z7.d, z2.d -; CHECK-NEXT: mov z7.h, z5.h[2] -; CHECK-NEXT: zip1 z3.d, z4.d, z3.d -; CHECK-NEXT: mov z4.h, z5.h[1] -; CHECK-NEXT: fcvtzu z19.d, p0/m, z19.h -; CHECK-NEXT: fcvtzu z20.d, p0/m, z20.h -; CHECK-NEXT: fcvtzu z21.d, p0/m, z21.h -; CHECK-NEXT: fcvtzu z18.d, p0/m, z18.h -; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.h -; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.h -; CHECK-NEXT: zip1 z0.d, z0.d, z17.d -; CHECK-NEXT: zip1 z1.d, z1.d, z16.d -; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.h -; CHECK-NEXT: stp q2, q1, [x1] -; CHECK-NEXT: stp q0, q3, [x1, #64] -; CHECK-NEXT: zip1 z0.d, z20.d, z19.d -; CHECK-NEXT: zip1 z3.d, z6.d, z21.d -; CHECK-NEXT: zip1 z1.d, z7.d, z18.d -; CHECK-NEXT: zip1 z2.d, z5.d, z4.d -; CHECK-NEXT: stp q3, q0, [x1, #96] -; CHECK-NEXT: stp q2, q1, [x1, #32] +; CHECK-NEXT: fcvtzu x10, h2 +; CHECK-NEXT: fcvtzu x11, h4 +; CHECK-NEXT: mov z16.h, z2.h[3] +; CHECK-NEXT: fcvtzu x9, h3 +; CHECK-NEXT: mov z3.h, z0.h[1] +; CHECK-NEXT: fcvtzu x12, h5 +; CHECK-NEXT: mov z5.h, z4.h[3] +; CHECK-NEXT: fcvtzu x13, h6 +; CHECK-NEXT: mov z6.h, z2.h[1] +; CHECK-NEXT: fcvtzu x14, h16 +; CHECK-NEXT: mov z16.h, z4.h[1] +; CHECK-NEXT: mov z4.h, z4.h[2] +; CHECK-NEXT: mov z2.h, z2.h[2] +; CHECK-NEXT: fcvtzu x15, h5 +; CHECK-NEXT: fmov d5, x10 +; CHECK-NEXT: fcvtzu x10, h0 +; CHECK-NEXT: fmov d0, x11 +; CHECK-NEXT: fcvtzu x11, h3 +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: fcvtzu x9, h7 +; CHECK-NEXT: fmov d7, x12 +; CHECK-NEXT: fcvtzu x12, h1 +; CHECK-NEXT: fmov d1, x13 +; CHECK-NEXT: fcvtzu x13, h6 +; CHECK-NEXT: fmov d6, x14 +; CHECK-NEXT: fcvtzu x14, h16 +; CHECK-NEXT: fmov d16, x15 +; CHECK-NEXT: fcvtzu x15, h4 +; CHECK-NEXT: fmov d4, x10 +; CHECK-NEXT: fcvtzu x10, h2 +; CHECK-NEXT: zip1 z1.d, z1.d, z7.d +; CHECK-NEXT: fmov d7, x11 +; CHECK-NEXT: fmov d2, x12 +; CHECK-NEXT: zip1 z4.d, z4.d, z7.d +; CHECK-NEXT: fmov d7, x8 +; CHECK-NEXT: zip1 z2.d, z2.d, z3.d +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: stp q4, q1, [x1, #64] +; CHECK-NEXT: fmov d1, x14 +; CHECK-NEXT: fmov d4, x10 +; CHECK-NEXT: zip1 z3.d, z7.d, z3.d +; CHECK-NEXT: fmov d7, x15 +; CHECK-NEXT: zip1 z0.d, z0.d, z1.d +; CHECK-NEXT: fmov d1, x13 +; CHECK-NEXT: zip1 z7.d, z7.d, z16.d +; CHECK-NEXT: stp q3, q2, [x1] +; CHECK-NEXT: zip1 z2.d, z4.d, z6.d +; CHECK-NEXT: zip1 z1.d, z5.d, z1.d +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: stp q1, q2, [x1, #32] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i64: @@ -2119,10 +2142,8 @@ define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) { define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) { ; CHECK-LABEL: fcvtzs_v1f16_v1i64: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: fcvtzs x8, h0 +; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzs_v1f16_v1i64: @@ -2144,9 +2165,10 @@ define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) { ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: mov z1.h, z0.h[1] -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h -; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h +; CHECK-NEXT: fcvtzs x8, h0 +; CHECK-NEXT: fcvtzs x9, h1 +; CHECK-NEXT: fmov d0, x8 +; CHECK-NEXT: fmov d1, x9 ; CHECK-NEXT: zip1 z0.d, z0.d, z1.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret @@ -2174,17 +2196,20 @@ define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) { ; CHECK-LABEL: fcvtzs_v4f16_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: mov z1.h, z0.h[3] ; CHECK-NEXT: mov z2.h, z0.h[2] ; CHECK-NEXT: mov z3.h, z0.h[1] -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h -; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h -; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h -; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h +; CHECK-NEXT: fcvtzs x10, h0 +; CHECK-NEXT: fcvtzs x8, h1 +; CHECK-NEXT: fcvtzs x9, h2 +; CHECK-NEXT: fcvtzs x11, h3 +; CHECK-NEXT: fmov d2, x10 +; CHECK-NEXT: fmov d0, x8 +; CHECK-NEXT: fmov d1, x9 +; CHECK-NEXT: zip1 z0.d, z1.d, z0.d +; CHECK-NEXT: fmov d1, x11 ; CHECK-NEXT: zip1 z1.d, z2.d, z1.d -; CHECK-NEXT: zip1 z0.d, z0.d, z3.d -; CHECK-NEXT: stp q0, q1, [x1] +; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i64: @@ -2221,29 +2246,36 @@ define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) { ; CHECK-LABEL: fcvtzs_v8f16_v8i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: mov z2.h, z0.h[3] ; CHECK-NEXT: mov z3.h, z0.h[2] ; CHECK-NEXT: mov z4.h, z0.h[1] ; CHECK-NEXT: movprfx z1, z0 ; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8 -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h -; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h -; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h -; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h +; CHECK-NEXT: fcvtzs x10, h0 +; CHECK-NEXT: fcvtzs x8, h2 +; CHECK-NEXT: fcvtzs x9, h3 +; CHECK-NEXT: fcvtzs x11, h4 ; CHECK-NEXT: mov z5.h, z1.h[3] ; CHECK-NEXT: mov z6.h, z1.h[2] -; CHECK-NEXT: mov z7.h, z1.h[1] -; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h -; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h -; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h -; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h -; CHECK-NEXT: zip1 z2.d, z3.d, z2.d -; CHECK-NEXT: zip1 z0.d, z0.d, z4.d -; CHECK-NEXT: zip1 z3.d, z6.d, z5.d -; CHECK-NEXT: zip1 z1.d, z1.d, z7.d -; CHECK-NEXT: stp q0, q2, [x1] -; CHECK-NEXT: stp q1, q3, [x1, #32] +; CHECK-NEXT: mov z2.h, z1.h[1] +; CHECK-NEXT: fcvtzs x14, h1 +; CHECK-NEXT: fcvtzs x12, h5 +; CHECK-NEXT: fcvtzs x13, h6 +; CHECK-NEXT: fmov d0, x8 +; CHECK-NEXT: fmov d1, x9 +; CHECK-NEXT: fcvtzs x15, h2 +; CHECK-NEXT: fmov d2, x10 +; CHECK-NEXT: fmov d3, x11 +; CHECK-NEXT: zip1 z0.d, z1.d, z0.d +; CHECK-NEXT: fmov d1, x12 +; CHECK-NEXT: fmov d4, x13 +; CHECK-NEXT: zip1 z2.d, z2.d, z3.d +; CHECK-NEXT: fmov d3, x14 +; CHECK-NEXT: zip1 z1.d, z4.d, z1.d +; CHECK-NEXT: fmov d4, x15 +; CHECK-NEXT: stp q2, q0, [x1] +; CHECK-NEXT: zip1 z3.d, z3.d, z4.d +; CHECK-NEXT: stp q3, q1, [x1, #32] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i64: @@ -2297,52 +2329,66 @@ define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) { ; CHECK-LABEL: fcvtzs_v16f16_v16i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mov z2.h, z1.h[1] -; CHECK-NEXT: mov z3.h, z0.h[3] -; CHECK-NEXT: mov z4.h, z0.h[2] -; CHECK-NEXT: movprfx z7, z1 -; CHECK-NEXT: fcvtzs z7.d, p0/m, z1.h -; CHECK-NEXT: movprfx z5, z1 -; CHECK-NEXT: ext z5.b, z5.b, z1.b, #8 -; CHECK-NEXT: movprfx z6, z0 -; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8 -; CHECK-NEXT: mov z16.h, z1.h[3] +; CHECK-NEXT: movprfx z2, z1 +; CHECK-NEXT: ext z2.b, z2.b, z1.b, #8 +; CHECK-NEXT: movprfx z4, z0 +; CHECK-NEXT: ext z4.b, z4.b, z0.b, #8 +; CHECK-NEXT: mov z3.h, z1.h[3] +; CHECK-NEXT: mov z5.h, z0.h[3] +; CHECK-NEXT: mov z6.h, z0.h[2] +; CHECK-NEXT: fcvtzs x8, h1 +; CHECK-NEXT: mov z7.h, z1.h[1] ; CHECK-NEXT: mov z1.h, z1.h[2] -; CHECK-NEXT: mov z17.h, z0.h[1] -; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h -; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h -; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h -; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h -; CHECK-NEXT: mov z18.h, z5.h[3] -; CHECK-NEXT: mov z19.h, z6.h[3] -; CHECK-NEXT: mov z20.h, z6.h[2] -; CHECK-NEXT: fcvtzs z17.d, p0/m, z17.h -; CHECK-NEXT: mov z21.h, z6.h[1] -; CHECK-NEXT: fcvtzs z16.d, p0/m, z16.h -; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h -; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h -; CHECK-NEXT: zip1 z2.d, z7.d, z2.d -; CHECK-NEXT: mov z7.h, z5.h[2] -; CHECK-NEXT: zip1 z3.d, z4.d, z3.d -; CHECK-NEXT: mov z4.h, z5.h[1] -; CHECK-NEXT: fcvtzs z19.d, p0/m, z19.h -; CHECK-NEXT: fcvtzs z20.d, p0/m, z20.h -; CHECK-NEXT: fcvtzs z21.d, p0/m, z21.h -; CHECK-NEXT: fcvtzs z18.d, p0/m, z18.h -; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h -; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h -; CHECK-NEXT: zip1 z0.d, z0.d, z17.d -; CHECK-NEXT: zip1 z1.d, z1.d, z16.d -; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h -; CHECK-NEXT: stp q2, q1, [x1] -; CHECK-NEXT: stp q0, q3, [x1, #64] -; CHECK-NEXT: zip1 z0.d, z20.d, z19.d -; CHECK-NEXT: zip1 z3.d, z6.d, z21.d -; CHECK-NEXT: zip1 z1.d, z7.d, z18.d -; CHECK-NEXT: zip1 z2.d, z5.d, z4.d -; CHECK-NEXT: stp q3, q0, [x1, #96] -; CHECK-NEXT: stp q2, q1, [x1, #32] +; CHECK-NEXT: fcvtzs x10, h2 +; CHECK-NEXT: fcvtzs x11, h4 +; CHECK-NEXT: mov z16.h, z2.h[3] +; CHECK-NEXT: fcvtzs x9, h3 +; CHECK-NEXT: mov z3.h, z0.h[1] +; CHECK-NEXT: fcvtzs x12, h5 +; CHECK-NEXT: mov z5.h, z4.h[3] +; CHECK-NEXT: fcvtzs x13, h6 +; CHECK-NEXT: mov z6.h, z2.h[1] +; CHECK-NEXT: fcvtzs x14, h16 +; CHECK-NEXT: mov z16.h, z4.h[1] +; CHECK-NEXT: mov z4.h, z4.h[2] +; CHECK-NEXT: mov z2.h, z2.h[2] +; CHECK-NEXT: fcvtzs x15, h5 +; CHECK-NEXT: fmov d5, x10 +; CHECK-NEXT: fcvtzs x10, h0 +; CHECK-NEXT: fmov d0, x11 +; CHECK-NEXT: fcvtzs x11, h3 +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: fcvtzs x9, h7 +; CHECK-NEXT: fmov d7, x12 +; CHECK-NEXT: fcvtzs x12, h1 +; CHECK-NEXT: fmov d1, x13 +; CHECK-NEXT: fcvtzs x13, h6 +; CHECK-NEXT: fmov d6, x14 +; CHECK-NEXT: fcvtzs x14, h16 +; CHECK-NEXT: fmov d16, x15 +; CHECK-NEXT: fcvtzs x15, h4 +; CHECK-NEXT: fmov d4, x10 +; CHECK-NEXT: fcvtzs x10, h2 +; CHECK-NEXT: zip1 z1.d, z1.d, z7.d +; CHECK-NEXT: fmov d7, x11 +; CHECK-NEXT: fmov d2, x12 +; CHECK-NEXT: zip1 z4.d, z4.d, z7.d +; CHECK-NEXT: fmov d7, x8 +; CHECK-NEXT: zip1 z2.d, z2.d, z3.d +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: stp q4, q1, [x1, #64] +; CHECK-NEXT: fmov d1, x14 +; CHECK-NEXT: fmov d4, x10 +; CHECK-NEXT: zip1 z3.d, z7.d, z3.d +; CHECK-NEXT: fmov d7, x15 +; CHECK-NEXT: zip1 z0.d, z0.d, z1.d +; CHECK-NEXT: fmov d1, x13 +; CHECK-NEXT: zip1 z7.d, z7.d, z16.d +; CHECK-NEXT: stp q3, q2, [x1] +; CHECK-NEXT: zip1 z2.d, z4.d, z6.d +; CHECK-NEXT: zip1 z1.d, z5.d, z1.d +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: stp q1, q2, [x1, #32] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i64: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll index 1901f24ef8167..1f2f4caab0a69 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll @@ -1102,9 +1102,10 @@ define <2 x half> @ucvtf_v2i64_v2f16(<2 x i64> %op1) { ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 ; CHECK-NEXT: mov z1.d, z0.d[1] -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d -; CHECK-NEXT: ucvtf z1.h, p0/m, z1.d +; CHECK-NEXT: fmov x8, d0 +; CHECK-NEXT: fmov x9, d1 +; CHECK-NEXT: ucvtf h0, x8 +; CHECK-NEXT: ucvtf h1, x9 ; CHECK-NEXT: zip1 z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -2511,9 +2512,10 @@ define <2 x half> @scvtf_v2i64_v2f16(<2 x i64> %op1) { ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 ; CHECK-NEXT: mov z1.d, z0.d[1] -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: scvtf z0.h, p0/m, z0.d -; CHECK-NEXT: scvtf z1.h, p0/m, z1.d +; CHECK-NEXT: fmov x8, d0 +; CHECK-NEXT: fmov x9, d1 +; CHECK-NEXT: scvtf h0, x8 +; CHECK-NEXT: scvtf h1, x9 ; CHECK-NEXT: zip1 z0.h, z0.h, z1.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -2709,10 +2711,7 @@ define half @scvtf_i16_f16(ptr %0) { ; CHECK-LABEL: scvtf_i16_f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrsh w8, [x0] -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: scvtf z0.h, p0/m, z0.s -; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: scvtf h0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: scvtf_i16_f16: @@ -2730,10 +2729,7 @@ define float @scvtf_i16_f32(ptr %0) { ; CHECK-LABEL: scvtf_i16_f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrsh w8, [x0] -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: scvtf z0.s, p0/m, z0.s -; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: scvtf s0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: scvtf_i16_f32: @@ -2766,10 +2762,8 @@ define double @scvtf_i16_f64(ptr %0) { define half @scvtf_i32_f16(ptr %0) { ; CHECK-LABEL: scvtf_i32_f16: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: ldr s0, [x0] -; CHECK-NEXT: scvtf z0.h, p0/m, z0.s -; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ldr w8, [x0] +; CHECK-NEXT: scvtf h0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: scvtf_i32_f16: @@ -2786,10 +2780,8 @@ define half @scvtf_i32_f16(ptr %0) { define float @scvtf_i32_f32(ptr %0) { ; CHECK-LABEL: scvtf_i32_f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: ldr s0, [x0] -; CHECK-NEXT: scvtf z0.s, p0/m, z0.s -; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ldr w8, [x0] +; CHECK-NEXT: scvtf s0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: scvtf_i32_f32: @@ -2822,10 +2814,8 @@ define double @scvtf_i32_f64(ptr %0) { define half @scvtf_i64_f16(ptr %0) { ; CHECK-LABEL: scvtf_i64_f16: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: scvtf z0.h, p0/m, z0.d -; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: scvtf h0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: scvtf_i64_f16: @@ -2842,10 +2832,8 @@ define half @scvtf_i64_f16(ptr %0) { define float @scvtf_i64_f32(ptr %0) { ; CHECK-LABEL: scvtf_i64_f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: scvtf z0.s, p0/m, z0.d -; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: scvtf s0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: scvtf_i64_f32: @@ -2861,10 +2849,8 @@ define float @scvtf_i64_f32(ptr %0) { define double @scvtf_i64_f64(ptr %0) { ; CHECK-LABEL: scvtf_i64_f64: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: scvtf z0.d, p0/m, z0.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: scvtf d0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: scvtf_i64_f64: @@ -2881,10 +2867,7 @@ define half @ucvtf_i16_f16(ptr %0) { ; CHECK-LABEL: ucvtf_i16_f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrh w8, [x0] -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s -; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ucvtf h0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: ucvtf_i16_f16: @@ -2902,10 +2885,7 @@ define float @ucvtf_i16_f32(ptr %0) { ; CHECK-LABEL: ucvtf_i16_f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldrh w8, [x0] -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s -; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ucvtf s0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: ucvtf_i16_f32: @@ -2938,10 +2918,8 @@ define double @ucvtf_i16_f64(ptr %0) { define half @ucvtf_i32_f16(ptr %0) { ; CHECK-LABEL: ucvtf_i32_f16: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: ldr s0, [x0] -; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s -; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ldr w8, [x0] +; CHECK-NEXT: ucvtf h0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: ucvtf_i32_f16: @@ -2958,10 +2936,8 @@ define half @ucvtf_i32_f16(ptr %0) { define float @ucvtf_i32_f32(ptr %0) { ; CHECK-LABEL: ucvtf_i32_f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: ldr s0, [x0] -; CHECK-NEXT: ucvtf z0.s, p0/m, z0.s -; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ldr w8, [x0] +; CHECK-NEXT: ucvtf s0, w8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: ucvtf_i32_f32: @@ -2994,10 +2970,8 @@ define double @ucvtf_i32_f64(ptr %0) { define half @ucvtf_i64_f16(ptr %0) { ; CHECK-LABEL: ucvtf_i64_f16: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: ucvtf z0.h, p0/m, z0.d -; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: ucvtf h0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: ucvtf_i64_f16: @@ -3014,10 +2988,8 @@ define half @ucvtf_i64_f16(ptr %0) { define float @ucvtf_i64_f32(ptr %0) { ; CHECK-LABEL: ucvtf_i64_f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d -; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: ucvtf s0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: ucvtf_i64_f32: @@ -3033,10 +3005,8 @@ define float @ucvtf_i64_f32(ptr %0) { define double @ucvtf_i64_f64(ptr %0) { ; CHECK-LABEL: ucvtf_i64_f64: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: ucvtf d0, x8 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: ucvtf_i64_f64: _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
