https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/179435
A recent specification update has removed FEAT_XS gating for `tlbip *nxs` instructions. It remains gated on FEAT_XS for `tlbi *nxs` instructions. >From 9f7c00eeeb6fa85df8bd788b1dd80294c2359d27 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Mon, 2 Feb 2026 15:56:06 +0000 Subject: [PATCH] [AArch64][llvm] Remove `+xs` gating for `tlbip *nxs` instructions A recent specification update has removed FEAT_XS gating for `tlbip *nxs` instructions. It remains gated on FEAT_XS for `tlbi *nxs` instructions. --- .../Target/AArch64/AArch64SystemOperands.td | 3 +-- .../AArch64/AsmParser/AArch64AsmParser.cpp | 22 +++++-------------- .../MCTargetDesc/AArch64InstPrinter.cpp | 8 ------- llvm/test/MC/AArch64/armv9a-sysp.s | 17 +++++++------- llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s | 4 ++-- 5 files changed, 17 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 86b2a2c37fcd3..335a50ae900ff 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -905,7 +905,6 @@ multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm defvar TLBIPRequires = !if(allowTLBID, ["AArch64::FeatureD128", "AArch64::FeatureTLBID"], ["AArch64::FeatureD128"]); - defvar TLBIPRequiresNXS = !listconcat(TLBIPRequires, ["AArch64::FeatureXS"]); def : TLBIEntry<name, op1, crn, crm, op2, needsreg, optionalreg>; def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg, optionalreg> { let Encoding{7} = 1; @@ -917,7 +916,7 @@ multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm } def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg, optionalreg> { let Encoding{7} = 1; - let ExtraRequires = TLBIPRequiresNXS; + let ExtraRequires = TLBIPRequires; } } } diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 8367eb4d54acf..f23da6a212c68 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -4262,23 +4262,13 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc, SMLoc S = Tok.getLoc(); if (Mnemonic == "tlbip") { - bool HasnXSQualifier = Op.ends_with_insensitive("nXS"); - if (HasnXSQualifier) { - Op = Op.drop_back(3); - } - const AArch64TLBIP::TLBIP *TLBIPorig = AArch64TLBIP::lookupTLBIPByName(Op); - if (!TLBIPorig) + const AArch64TLBIP::TLBIP *TLBIP = AArch64TLBIP::lookupTLBIPByName(Op); + if (!TLBIP) return TokError("invalid operand for TLBIP instruction"); - const AArch64TLBIP::TLBIP TLBIP( - TLBIPorig->Name, TLBIPorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0), - TLBIPorig->NeedsReg, TLBIPorig->OptionalReg, - HasnXSQualifier - ? TLBIPorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS}) - : TLBIPorig->FeaturesRequired); - if (!TLBIP.haveFeatures(getSTI().getFeatureBits())) { + if (!TLBIP->haveFeatures(getSTI().getFeatureBits())) { FeatureBitset Active = getSTI().getFeatureBits(); - FeatureBitset Missing = TLBIP.getRequiredFeatures() & ~Active; - if (TLBIP.allowTLBID()) { + FeatureBitset Missing = TLBIP->getRequiredFeatures() & ~Active; + if (TLBIP->allowTLBID()) { Missing.reset(AArch64::FeatureD128); Missing.reset(AArch64::FeatureTLBID); if (!Active[AArch64::FeatureD128] && !Active[AArch64::FeatureTLBID]) { @@ -4292,7 +4282,7 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc, setRequiredFeatureString(Missing, Str); return TokError(Str); } - createSysAlias(TLBIP.Encoding, Operands, S); + createSysAlias(TLBIP->Encoding, Operands, S); } Lex(); // Eat operand. diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 3e4c1101fb8e1..2fe162f930fdf 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1163,12 +1163,6 @@ bool AArch64InstPrinter::printSyspAlias(const MCInst *MI, if (CnVal == 8 || CnVal == 9) { // TLBIP aliases - if (CnVal == 9) { - if (!STI.hasFeature(AArch64::FeatureXS)) - return false; - Encoding &= ~(1 << 7); - } - const AArch64TLBIP::TLBIP *TLBIP = AArch64TLBIP::lookupTLBIPByEncoding(Encoding); if (!TLBIP || !TLBIP->haveFeatures(STI.getFeatureBits())) @@ -1176,8 +1170,6 @@ bool AArch64InstPrinter::printSyspAlias(const MCInst *MI, Ins = "tlbip\t"; Name = std::string(TLBIP->Name); - if (CnVal == 9) - Name += "nXS"; } else return false; diff --git a/llvm/test/MC/AArch64/armv9a-sysp.s b/llvm/test/MC/AArch64/armv9a-sysp.s index 1d81698f32001..3dbbfb7091b4f 100644 --- a/llvm/test/MC/AArch64/armv9a-sysp.s +++ b/llvm/test/MC/AArch64/armv9a-sysp.s @@ -1,20 +1,19 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi,+xs < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+tlb-rmi,+xs < %s 2>&1 \ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+tlb-rmi < %s 2>&1 \ // RUN: | FileCheck %s --check-prefixes=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi,+xs < %s \ -// RUN: | llvm-objdump -d --mattr=+d128,+tlb-rmi,+xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi,+xs < %s \ -// RUN: | llvm-objdump -d --mattr=-d128,+tlb-rmi,+xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi < %s \ +// RUN: | llvm-objdump -d --mattr=+d128,+tlb-rmi --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi < %s \ +// RUN: | llvm-objdump -d --mattr=-d128,+tlb-rmi --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN // Disassemble encoding and check the re-encoding (-show-encoding) matches. -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi,+xs < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+tlb-rmi,+xs -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+tlb-rmi -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // +tbl-rmi required for RIPA*/RVA* -// +xs required for *NXS // sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} // registers with 128-bit formats (op0, op1, Cn, Cm, op2) diff --git a/llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s b/llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s index 0361fbcc73d4b..2baeda54bb0a7 100644 --- a/llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s +++ b/llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s @@ -1,6 +1,6 @@ // NOTE: These TLBIP forms are valid with either +tlbid or +d128. -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbid,+tlb-rmi,+xs < %s | FileCheck %s --check-prefix=TLBID -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi,+xs < %s | FileCheck %s --check-prefix=D128 +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbid,+tlb-rmi < %s | FileCheck %s --check-prefix=TLBID +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi < %s | FileCheck %s --check-prefix=D128 tlbip VAE1OS, x0, x1 // TLBID: tlbip vae1os, x0, x1 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
