https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/179441
>From f0b184ab68f74fa29da35dbc4aacc624fd0b38d7 Mon Sep 17 00:00:00 2001 From: Petar Avramovic <[email protected]> Date: Tue, 3 Feb 2026 12:41:25 +0100 Subject: [PATCH] AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize Used to fail EXPENSIVE_CHECKS because of type mismatch. --- llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 8 +++++--- .../AMDGPU/GlobalISel/regbankselect-unmerge-values.mir | 8 ++++---- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp index 445150d9dfe5e..4f4f1cbf2b0d6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp @@ -1044,9 +1044,11 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI, B.setInstrAndDebugLoc(MI); if (Ty.getSizeInBits() > 32) { - auto Unmerge32 = B.buildUnmerge(SgprRB_S32, Unmerge->getSourceReg()); - for (unsigned i = 0; i < Unmerge32->getNumDefs(); ++i) { - auto [Dst0S32, Dst1S32] = unpackAExt(Unmerge32->getOperand(i).getReg()); + auto UnmergeV2S16 = + B.buildUnmerge({SgprRB, V2S16}, Unmerge->getSourceReg()); + for (unsigned i = 0; i < UnmergeV2S16->getNumDefs(); ++i) { + auto [Dst0S32, Dst1S32] = + unpackAExt(UnmergeV2S16->getOperand(i).getReg()); B.buildTrunc(MI.getOperand(i * 2).getReg(), Dst0S32); B.buildTrunc(MI.getOperand(i * 2 + 1).getReg(), Dst1S32); } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir index db0a9464b113e..746103bf181ca 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize -verify-machineinstrs %s -o - | FileCheck %s --- name: test_unmerge_s64_s32_s @@ -102,13 +102,13 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3 - ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) - ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV]](s32) + ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(<2 x s16>), [[UV1:%[0-9]+]]:sgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV]](<2 x s16>) ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST]](s32) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32) - ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV1]](s32) + ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV1]](<2 x s16>) ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST1]](s32) ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR1]](s32) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
