llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Paul Kirth (ilovepi) <details> <summary>Changes</summary> Fuchsia no longer supports TLS access via __tls_get_addr, and only supports the TLSDESC ABI on all target machines. Though we already set Fuchsia as enabling TLSDESC by default, LLD's LTO pipeline is initialized with an empty target triple, and thus does not correctly select the correct codegen options for Fuchsia's ABI. Instead, we can additionally check if Fuchsia is the actual target if the option isn't set, since useTLSDESC() is only called later, when a non-default target triple will be available. The alternative is to rework how LLD initializes the LTO code generation options, so that it selects the correct target, and initializes them correctly. However, that's a more invasive change, and would need some discussion to make sure that is handled correctly across all of LLDs supported formats (e.g. ELF, Mach-O, COFF, etc.). --- Full diff: https://github.com/llvm/llvm-project/pull/179509.diff 3 Files Affected: - (modified) llvm/lib/Target/TargetMachine.cpp (+3-1) - (modified) llvm/test/CodeGen/RISCV/tls-models.ll (+69) - (modified) llvm/test/CodeGen/X86/tls-desc.ll (+43) ``````````diff diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index f8f13a042fec0..3f59b819ffbf1 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -257,7 +257,9 @@ bool TargetMachine::shouldAssumeDSOLocal(const GlobalValue *GV) const { } bool TargetMachine::useEmulatedTLS() const { return Options.EmulatedTLS; } -bool TargetMachine::useTLSDESC() const { return Options.EnableTLSDESC; } +bool TargetMachine::useTLSDESC() const { + return Options.EnableTLSDESC || TargetTriple.isOSFuchsia(); +} TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const { bool IsPIE = GV->getParent()->getPIELevel() != PIELevel::Default; diff --git a/llvm/test/CodeGen/RISCV/tls-models.ll b/llvm/test/CodeGen/RISCV/tls-models.ll index 52c2c31d8fa81..8caa6108ffbe9 100644 --- a/llvm/test/CodeGen/RISCV/tls-models.ll +++ b/llvm/test/CodeGen/RISCV/tls-models.ll @@ -7,10 +7,13 @@ ; RUN: | FileCheck -check-prefix=RV64-PIC %s ; RUN: llc -mtriple=riscv64 -relocation-model=pic -enable-tlsdesc < %s \ ; RUN: | FileCheck -check-prefix=RV64-PIC-TLSDESC %s +; RUN: llc -mtriple=riscv64-unknown-fuchsia -relocation-model=pic < %s \ +; RUN: | FileCheck -check-prefix=RV64-PIC-FUCHSIA %s ; RUN: llc -mtriple=riscv32 < %s | FileCheck -check-prefix=RV32-NOPIC %s ; RUN: llc -mtriple=riscv32 < %s -enable-tlsdesc | FileCheck -check-prefix=RV32-NOPIC-TLSDESC %s ; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64-NOPIC %s ; RUN: llc -mtriple=riscv64 < %s -enable-tlsdesc | FileCheck -check-prefix=RV64-NOPIC-TLSDESC %s +; RUN: llc -mtriple=riscv64-unknown-fuchsia < %s | FileCheck -check-prefix=RV64-NOPIC-FUCHSIA %s ; Check that TLS symbols are lowered correctly based on the specified ; model. Make sure they're external to avoid them all being optimised to Local @@ -69,6 +72,16 @@ define ptr @f1() nounwind { ; RV64-PIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-PIC-TLSDESC-NEXT: ret ; +; RV64-PIC-FUCHSIA-LABEL: f1: +; RV64-PIC-FUCHSIA: # %bb.0: # %entry +; RV64-PIC-FUCHSIA-NEXT: .Ltlsdesc_hi0: +; RV64-PIC-FUCHSIA-NEXT: auipc a0, %tlsdesc_hi(unspecified) +; RV64-PIC-FUCHSIA-NEXT: ld a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0) +; RV64-PIC-FUCHSIA-NEXT: addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0) +; RV64-PIC-FUCHSIA-NEXT: jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0) +; RV64-PIC-FUCHSIA-NEXT: add a0, a0, tp +; RV64-PIC-FUCHSIA-NEXT: ret +; ; RV32-NOPIC-LABEL: f1: ; RV32-NOPIC: # %bb.0: # %entry ; RV32-NOPIC-NEXT: .Lpcrel_hi0: @@ -100,6 +113,14 @@ define ptr @f1() nounwind { ; RV64-NOPIC-TLSDESC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) ; RV64-NOPIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-NOPIC-TLSDESC-NEXT: ret +; +; RV64-NOPIC-FUCHSIA-LABEL: f1: +; RV64-NOPIC-FUCHSIA: # %bb.0: # %entry +; RV64-NOPIC-FUCHSIA-NEXT: .Lpcrel_hi0: +; RV64-NOPIC-FUCHSIA-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified) +; RV64-NOPIC-FUCHSIA-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) +; RV64-NOPIC-FUCHSIA-NEXT: add a0, a0, tp +; RV64-NOPIC-FUCHSIA-NEXT: ret entry: ret ptr @unspecified } @@ -152,6 +173,16 @@ define ptr @f2() nounwind { ; RV64-PIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-PIC-TLSDESC-NEXT: ret ; +; RV64-PIC-FUCHSIA-LABEL: f2: +; RV64-PIC-FUCHSIA: # %bb.0: # %entry +; RV64-PIC-FUCHSIA-NEXT: .Ltlsdesc_hi1: +; RV64-PIC-FUCHSIA-NEXT: auipc a0, %tlsdesc_hi(ld) +; RV64-PIC-FUCHSIA-NEXT: ld a1, %tlsdesc_load_lo(.Ltlsdesc_hi1)(a0) +; RV64-PIC-FUCHSIA-NEXT: addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi1) +; RV64-PIC-FUCHSIA-NEXT: jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi1) +; RV64-PIC-FUCHSIA-NEXT: add a0, a0, tp +; RV64-PIC-FUCHSIA-NEXT: ret +; ; RV32-NOPIC-LABEL: f2: ; RV32-NOPIC: # %bb.0: # %entry ; RV32-NOPIC-NEXT: .Lpcrel_hi1: @@ -183,6 +214,14 @@ define ptr @f2() nounwind { ; RV64-NOPIC-TLSDESC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0) ; RV64-NOPIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-NOPIC-TLSDESC-NEXT: ret +; +; RV64-NOPIC-FUCHSIA-LABEL: f2: +; RV64-NOPIC-FUCHSIA: # %bb.0: # %entry +; RV64-NOPIC-FUCHSIA-NEXT: .Lpcrel_hi1: +; RV64-NOPIC-FUCHSIA-NEXT: auipc a0, %tls_ie_pcrel_hi(ld) +; RV64-NOPIC-FUCHSIA-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0) +; RV64-NOPIC-FUCHSIA-NEXT: add a0, a0, tp +; RV64-NOPIC-FUCHSIA-NEXT: ret entry: ret ptr @ld } @@ -223,6 +262,14 @@ define ptr @f3() nounwind { ; RV64-PIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-PIC-TLSDESC-NEXT: ret ; +; RV64-PIC-FUCHSIA-LABEL: f3: +; RV64-PIC-FUCHSIA: # %bb.0: # %entry +; RV64-PIC-FUCHSIA-NEXT: .Lpcrel_hi0: +; RV64-PIC-FUCHSIA-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) +; RV64-PIC-FUCHSIA-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) +; RV64-PIC-FUCHSIA-NEXT: add a0, a0, tp +; RV64-PIC-FUCHSIA-NEXT: ret +; ; RV32-NOPIC-LABEL: f3: ; RV32-NOPIC: # %bb.0: # %entry ; RV32-NOPIC-NEXT: .Lpcrel_hi2: @@ -254,6 +301,14 @@ define ptr @f3() nounwind { ; RV64-NOPIC-TLSDESC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0) ; RV64-NOPIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-NOPIC-TLSDESC-NEXT: ret +; +; RV64-NOPIC-FUCHSIA-LABEL: f3: +; RV64-NOPIC-FUCHSIA: # %bb.0: # %entry +; RV64-NOPIC-FUCHSIA-NEXT: .Lpcrel_hi2: +; RV64-NOPIC-FUCHSIA-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) +; RV64-NOPIC-FUCHSIA-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0) +; RV64-NOPIC-FUCHSIA-NEXT: add a0, a0, tp +; RV64-NOPIC-FUCHSIA-NEXT: ret entry: ret ptr @ie } @@ -290,6 +345,13 @@ define ptr @f4() nounwind { ; RV64-PIC-TLSDESC-NEXT: addi a0, a0, %tprel_lo(le) ; RV64-PIC-TLSDESC-NEXT: ret ; +; RV64-PIC-FUCHSIA-LABEL: f4: +; RV64-PIC-FUCHSIA: # %bb.0: # %entry +; RV64-PIC-FUCHSIA-NEXT: lui a0, %tprel_hi(le) +; RV64-PIC-FUCHSIA-NEXT: add a0, a0, tp, %tprel_add(le) +; RV64-PIC-FUCHSIA-NEXT: addi a0, a0, %tprel_lo(le) +; RV64-PIC-FUCHSIA-NEXT: ret +; ; RV32-NOPIC-LABEL: f4: ; RV32-NOPIC: # %bb.0: # %entry ; RV32-NOPIC-NEXT: lui a0, %tprel_hi(le) @@ -317,6 +379,13 @@ define ptr @f4() nounwind { ; RV64-NOPIC-TLSDESC-NEXT: add a0, a0, tp, %tprel_add(le) ; RV64-NOPIC-TLSDESC-NEXT: addi a0, a0, %tprel_lo(le) ; RV64-NOPIC-TLSDESC-NEXT: ret +; +; RV64-NOPIC-FUCHSIA-LABEL: f4: +; RV64-NOPIC-FUCHSIA: # %bb.0: # %entry +; RV64-NOPIC-FUCHSIA-NEXT: lui a0, %tprel_hi(le) +; RV64-NOPIC-FUCHSIA-NEXT: add a0, a0, tp, %tprel_add(le) +; RV64-NOPIC-FUCHSIA-NEXT: addi a0, a0, %tprel_lo(le) +; RV64-NOPIC-FUCHSIA-NEXT: ret entry: ret ptr @le } diff --git a/llvm/test/CodeGen/X86/tls-desc.ll b/llvm/test/CodeGen/X86/tls-desc.ll index c73986e69e791..f7dc0ceeeeb32 100644 --- a/llvm/test/CodeGen/X86/tls-desc.ll +++ b/llvm/test/CodeGen/X86/tls-desc.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -mtriple=i686 --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=x86_64 --relocation-model=pic -enable-tlsdesc | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown-fuchsia --relocation-model=pic | FileCheck %s --check-prefix=X64-FUCHSIA @x = thread_local global i32 0, align 4 @y = internal thread_local global i32 1, align 4 @@ -62,6 +63,19 @@ define ptr @f1() nounwind { ; X64-NEXT: #NO_APP ; X64-NEXT: popq %rcx ; X64-NEXT: retq +; +; X64-FUCHSIA-LABEL: f1: +; X64-FUCHSIA: # %bb.0: +; X64-FUCHSIA-NEXT: pushq %rax +; X64-FUCHSIA-NEXT: #APP +; X64-FUCHSIA-NEXT: #NO_APP +; X64-FUCHSIA-NEXT: leaq x@tlsdesc(%rip), %rax +; X64-FUCHSIA-NEXT: callq *x@tlscall(%rax) +; X64-FUCHSIA-NEXT: addq %fs:0, %rax +; X64-FUCHSIA-NEXT: #APP +; X64-FUCHSIA-NEXT: #NO_APP +; X64-FUCHSIA-NEXT: popq %rcx +; X64-FUCHSIA-NEXT: retq %a = call { i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=r,=r,=r,=r,=r,=r,~{dirflag},~{fpsr},~{flags}"() %b = call ptr @llvm.threadlocal.address.p0(ptr @x) %a.0 = extractvalue { i32, i32, i32, i32, i32, i32 } %a, 0 @@ -109,6 +123,15 @@ define i32 @f2() nounwind { ; X64-NEXT: movl (%rax,%rcx), %eax ; X64-NEXT: popq %rcx ; X64-NEXT: retq +; +; X64-FUCHSIA-LABEL: f2: +; X64-FUCHSIA: # %bb.0: +; X64-FUCHSIA-NEXT: pushq %rax +; X64-FUCHSIA-NEXT: leaq x@tlsdesc(%rip), %rax +; X64-FUCHSIA-NEXT: callq *x@tlscall(%rax) +; X64-FUCHSIA-NEXT: movl %fs:(%rax), %eax +; X64-FUCHSIA-NEXT: popq %rcx +; X64-FUCHSIA-NEXT: retq %1 = tail call ptr @llvm.threadlocal.address.p0(ptr @x) %2 = load i32, ptr %1 ret i32 %2 @@ -147,6 +170,15 @@ define ptr @f3() nounwind { ; X64-NEXT: addq %fs:0, %rax ; X64-NEXT: popq %rcx ; X64-NEXT: retq +; +; X64-FUCHSIA-LABEL: f3: +; X64-FUCHSIA: # %bb.0: +; X64-FUCHSIA-NEXT: pushq %rax +; X64-FUCHSIA-NEXT: leaq x@tlsdesc(%rip), %rax +; X64-FUCHSIA-NEXT: callq *x@tlscall(%rax) +; X64-FUCHSIA-NEXT: addq %fs:0, %rax +; X64-FUCHSIA-NEXT: popq %rcx +; X64-FUCHSIA-NEXT: retq %1 = tail call ptr @llvm.threadlocal.address.p0(ptr @x) ret ptr %1 } @@ -192,6 +224,17 @@ define i32 @f4() nounwind { ; X64-NEXT: movl %ecx, %eax ; X64-NEXT: popq %rcx ; X64-NEXT: retq +; +; X64-FUCHSIA-LABEL: f4: +; X64-FUCHSIA: # %bb.0: +; X64-FUCHSIA-NEXT: pushq %rax +; X64-FUCHSIA-NEXT: leaq _TLS_MODULE_BASE_@tlsdesc(%rip), %rax +; X64-FUCHSIA-NEXT: callq *_TLS_MODULE_BASE_@tlscall(%rax) +; X64-FUCHSIA-NEXT: movl %fs:y@DTPOFF(%rax), %ecx +; X64-FUCHSIA-NEXT: addl %fs:z@DTPOFF(%rax), %ecx +; X64-FUCHSIA-NEXT: movl %ecx, %eax +; X64-FUCHSIA-NEXT: popq %rcx +; X64-FUCHSIA-NEXT: retq %1 = load i32, ptr @y, align 4 %2 = load i32, ptr @z, align 4 %3 = add nsw i32 %1, %2 `````````` </details> https://github.com/llvm/llvm-project/pull/179509 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
