llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-powerpc Author: Lei Huang (lei137) <details> <summary>Changes</summary> Add extended mnemonics to paddis. ``` paddis RT,RA,SI -> paddis RT,RA,SI,0 plis RT,SI -> paddis RT,0,SI,0 psubis RT,RA,si -> paddis RT,RA,-si,0 ``` --- Full diff: https://github.com/llvm/llvm-project/pull/179979.diff 8 Files Affected: - (modified) llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (+8) - (modified) llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp (+11) - (modified) llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h (+2) - (modified) llvm/lib/Target/PowerPC/PPCInstrFuture.td (+9) - (modified) llvm/lib/Target/PowerPC/PPCOperands.td (+21) - (modified) llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt (+1-1) - (modified) llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt (+1-1) - (modified) llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s (+26-2) ``````````diff diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index b07f95018ca90..13408cb8628e0 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -640,6 +640,14 @@ struct PPCOperand : public MCParsedAsmOperand { } } + void addNegImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + if (Kind == Immediate) + Inst.addOperand(MCOperand::createImm(-getImm())); + else + Inst.addOperand(MCOperand::createExpr(getExpr())); + } + void addBranchTargetOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); if (Kind == Immediate) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 46d6093be3c17..bbd604ad59175 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -441,6 +441,17 @@ void PPCInstPrinter::printS32ImmOperand(const MCInst *MI, unsigned OpNo, printOperand(MI, OpNo, STI, O); } +void PPCInstPrinter::printNegS32ImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (MI->getOperand(OpNo).isImm()) { + long long Value = MI->getOperand(OpNo).getImm(); + assert(isInt<32>(Value) && "Invalid s32imm argument!"); + O << (long long)Value; + } else + printOperand(MI, OpNo, STI, O); +} + void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 2fbd06c5a96cf..93b9526626c20 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -82,6 +82,8 @@ class PPCInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); void printS32ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printNegS32ImmOperand(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printU16ImmOperand(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index eb56fea8c9888..777c16a06d21d 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -605,6 +605,15 @@ let Predicates = [HasVSX, IsISAFuture] in { // Predicate combinations available: // [HasVSX, IsISAFuture] +def : InstAlias<"paddis $RT, $RA, $SI", (PADDIS gprc:$RT, gprc_nor0:$RA, + s32imm:$SI)>; +def : InstAlias<"paddis $RT, $RA, $SI", (PADDIS8 g8rc:$RT, g8rc_nox0:$RA, + s32imm64:$SI)>; +def : InstAlias<"plis $RT, $SI", (PADDIS gprc:$RT, ZERO, s32imm:$SI)>; +def : InstAlias<"plis $RT, $SI", (PADDIS8 g8rc:$RT, ZERO8, s32imm64:$SI)>; +def : InstAlias<"psubis $RT, $SI", (PADDIS gprc:$RT, ZERO, neg_s32imm:$SI)>; +def : InstAlias<"psubis $RT, $SI", (PADDIS8 g8rc:$RT, ZERO8, neg_s32imm64:$SI)>; + let Predicates = [HasVSX, IsISAFuture] in { def : InstAlias<"xxaes128encp $XTp, $XAp, $XBp", (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>; diff --git a/llvm/lib/Target/PowerPC/PPCOperands.td b/llvm/lib/Target/PowerPC/PPCOperands.td index 2b995cfe4190c..e9556c53cfd8e 100644 --- a/llvm/lib/Target/PowerPC/PPCOperands.td +++ b/llvm/lib/Target/PowerPC/PPCOperands.td @@ -84,6 +84,16 @@ multiclass SignedImmediateWithPCRel<ValueType vt, code pred, defm _pcrel : SignedImmediate<vt, pred, xform, asmop, width, fixup_pcrel>; } +//===----------------------------------------------------------------------===// +// Immediate transformation functions +//===----------------------------------------------------------------------===// + +// NEG_S32 - Negate a signed 32-bit immediate value +def NEG_S32 : SDNodeXForm<imm, [{ + // Transformation function: -imm + return getI32Imm(-N->getSExtValue(), SDLoc(N)); +}]>; + //===----------------------------------------------------------------------===// // Immediate AsmOperand definitions //===----------------------------------------------------------------------===// @@ -107,6 +117,7 @@ def S16Imm : ImmediateAsmOperand<"isS16Imm","addS16ImmOperands">; def S17Imm : ImmediateAsmOperand<"isS17Imm","addS16ImmOperands">; def S32Imm : ImmediateAsmOperand<"isS32Imm">; def S34Imm : ImmediateAsmOperand<"isS34Imm">; +def NegS32Imm : ImmediateAsmOperand<"isS32Imm","addNegImmOperands">; //===----------------------------------------------------------------------===// // i32 immediate operands @@ -147,9 +158,15 @@ defm s5imm : SignedImmediate<i32, [{ return isInt<5>(Imm); }], NOOP_SDNodeXForm, "S5Imm", 5>; +defm s32imm : SignedImmediate<i32, + [{ return isInt<32>(Imm); }], NOOP_SDNodeXForm, + "S32Imm", 32, "PPC::fixup_ppc_imm32">; defm s34imm : SignedImmediate<i32, [{ return isInt<34>(Imm); }], NOOP_SDNodeXForm, "S34Imm", 34, "PPC::fixup_ppc_imm34">; +defm neg_s32imm : SignedImmediate<i32, + [{ return isInt<32>(Imm); }], NEG_S32, + "NegS32Imm", 32, "PPC::fixup_ppc_imm32">; //===----------------------------------------------------------------------===// // i64 immediate operands @@ -161,6 +178,10 @@ defm s32imm64 : SignedImmediateWithPCRel<i64, defm s34imm64 : SignedImmediateWithPCRel<i64, [{ return isInt<34>(Imm); }], NOOP_SDNodeXForm, "S34Imm", 34, "PPC::fixup_ppc_imm34", "PPC::fixup_ppc_pcrel34">; +defm neg_s32imm64 : SignedImmediate<i64, + [{ return isInt<32>(Imm); }], NEG_S32, + "NegS32Imm", 32, "PPC::fixup_ppc_imm32">; + //===----------------------------------------------------------------------===// // Special case immediate operands diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index 1024c6b546c4a..a93b920c80cd7 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -298,7 +298,7 @@ #CHECK: mtlpl 3, 4 0x7c,0x80,0x1a,0x26 -#CHECK: paddis 10, 12, 1000000000, 0 +#CHECK: paddis 10, 12, 1000000000 0x06,0x00,0x3b,0x9a,0x3d,0x4c,0xca,0x00 #CHECK: paddis 10, 0, 1000000000, 1 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index bda8d1e69442f..2a1077c159845 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -292,7 +292,7 @@ #CHECK: mtlpl 3, 4 0x26,0x1a,0x80,0x7c -#CHECK: paddis 10, 12, 1000000000, 0 +#CHECK: paddis 10, 12, 1000000000 0x9a,0x3b,0x00,0x06,0x00,0xca,0x4c,0x3d #CHECK: paddis 10, 0, 1000000000, 1 diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index eb616a15500f1..1868bb0f07244 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -419,10 +419,16 @@ #CHECK-BE: mtlpl 3, 4 # encoding: [0x7c,0x80,0x1a,0x26] #CHECK-LE: mtlpl 3, 4 # encoding: [0x26,0x1a,0x80,0x7c] + paddis 10, 12, 1000000000 +#CHECK-BE: paddis 10, 12, 1000000000 # encoding: [0x06,0x00,0x3b,0x9a, +#CHECK-BE-SAME: 0x3d,0x4c,0xca,0x00] +#CHECK-LE: paddis 10, 12, 1000000000 # encoding: [0x9a,0x3b,0x00,0x06, +#CHECK-LE-SAME: 0x00,0xca,0x4c,0x3d] + paddis 10, 12, 1000000000, 0 -#CHECK-BE: paddis 10, 12, 1000000000, 0 # encoding: [0x06,0x00,0x3b,0x9a, +#CHECK-BE: paddis 10, 12, 1000000000 # encoding: [0x06,0x00,0x3b,0x9a, #CHECK-BE-SAME: 0x3d,0x4c,0xca,0x00] -#CHECK-LE: paddis 10, 12, 1000000000, 0 # encoding: [0x9a,0x3b,0x00,0x06, +#CHECK-LE: paddis 10, 12, 1000000000 # encoding: [0x9a,0x3b,0x00,0x06, #CHECK-LE-SAME: 0x00,0xca,0x4c,0x3d] paddis 10, 0, 1000000000, 1 @@ -431,6 +437,24 @@ #CHECK-LE: paddis 10, 0, 1000000000, 1 # encoding: [0x9a,0x3b,0x10,0x06, #CHECK-LE-SAME: 0x00,0xca,0x40,0x3d] + plis 10, 1000000000 +#CHECK-BE: paddis 10, 0, 1000000000 # encoding: [0x06,0x00,0x3b,0x9a, +#CHECK-BE-SAME: 0x3d,0x40,0xca,0x00] +#CHECK-LE: paddis 10, 0, 1000000000 # encoding: [0x9a,0x3b,0x00,0x06, +#CHECK-LE-SAME: 0x00,0xca,0x40,0x3d] + + psubis 10, 1000000000 +#CHECK-BE: paddis 10, 0, -1000000000 # encoding: [0x06,0x00,0xc4,0x65, +#CHECK-BE-SAME: 0x3d,0x40,0x36,0x00] +#CHECK-LE: paddis 10, 0, -1000000000 # encoding: [0x65,0xc4,0x00,0x06, +#CHECK-LE-SAME: 0x00,0x36,0x40,0x3d] + + psubis 10, -1000000000 +#CHECK-BE: paddis 10, 0, 1000000000 # encoding: [0x06,0x00,0x3b,0x9a, +#CHECK-BE-SAME: 0x3d,0x40,0xca,0x00] +#CHECK-LE: paddis 10, 0, 1000000000 # encoding: [0x9a,0x3b,0x00,0x06, +#CHECK-LE-SAME: 0x00,0xca,0x40,0x3d] + xxmulmul 8, 3, 4, 2 #CHECK-BE: xxmulmul 8, 3, 4, 2 # encoding: [0xed,0x03,0x22,0x08] #CHECK-LE: xxmulmul 8, 3, 4, 2 # encoding: [0x08,0x22,0x03,0xed] `````````` </details> https://github.com/llvm/llvm-project/pull/179979 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
