================
@@ -44,10 +43,23 @@ multiclass PseudoVABS {
}
}
+multiclass VPseudoVWABD_VV {
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defm "" : VPseudoTernaryW_VV<m, Commutable = 1>,
+ SchedTernary<"WriteVIWMulAddV", "ReadVIWMulAddV",
+ "ReadVIWMulAddV", "ReadVIWMulAddV", mx>;
+ }
+}
+
let Predicates = [HasStdExtZvabd] in {
defm PseudoVABS : PseudoVABS;
defm PseudoVABD : VPseudoVALU_VV<Commutable = 1>;
defm PseudoVABDU : VPseudoVALU_VV<Commutable = 1>;
+ let IsRVVWideningReduction = 1 in {
----------------
wangpc-pp wrote:
The semantics is:
> This instruction computes the absolute difference between the elements of two
> signed/unsigned integer
SEW-bit source operands vs1 and vs2, and accumulates the results into the
elements of a 2*SEW bit integer operand vd.
>From what I see, it is `vd[0] = sum(vd[0], abd<u>(vs1 , vs2)`, just like
>`vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] )`. And I checked
>how `IsRVVWideningReduction ` is used:
>https://github.com/llvm/llvm-project/blob/bd4784a913cd53f42ff8c2a3ddfff2e106c5070a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp#L353-L364
I think it should match?
https://github.com/llvm/llvm-project/pull/180162
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