llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: Jonathan Thackray (jthackray) <details> <summary>Changes</summary> Skip the SVE scalar-combine for saturating FP->INT when the scalar op is legal, so we use simpler scalar codegen in streaming modes. --- Patch is 99.45 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/180932.diff 2 Files Affected: - (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+9) - (modified) llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll (+120-1585) ``````````diff diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 47242e72921c0..9b68dc0e210c5 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -20637,6 +20637,15 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG, if (!isSupportedType(SrcTy) || !isSupportedType(DestTy)) return SDValue(); + if (N->getOpcode() == ISD::FP_TO_SINT_SAT || + N->getOpcode() == ISD::FP_TO_UINT_SAT) { + // Keep scalar/custom lowering when the target already + // handles saturating conversion for this type. + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (TLI.isOperationLegalOrCustom(N->getOpcode(), DestTy)) + return SDValue(); + } + EVT SrcVecTy; EVT DestVecTy; if (DestTy.bitsGT(SrcTy)) { diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll index 441da38fe15fc..7dd0806758d28 100644 --- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll +++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll @@ -1928,42 +1928,12 @@ define float @fcvtzs_sh_sat_simd(half %a) { ; ; CHECK-SME-LABEL: fcvtzs_sh_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: adrp x8, .LCPI64_1 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI64_1 -; CHECK-SME-NEXT: ld1rh { z1.s }, p0/z, [x8] -; CHECK-SME-NEXT: adrp x8, .LCPI64_0 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI64_0 -; CHECK-SME-NEXT: ld1rh { z2.s }, p0/z, [x8] -; CHECK-SME-NEXT: fcmge p1.h, p0/z, z0.h, z1.h -; CHECK-SME-NEXT: mov z1.s, #0x80000000 -; CHECK-SME-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h -; CHECK-SME-NEXT: mov z2.s, #0x7fffffff -; CHECK-SME-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h -; CHECK-SME-NEXT: fcvtzs z1.s, p1/m, z0.h -; CHECK-SME-NEXT: sel z0.s, p2, z2.s, z1.s -; CHECK-SME-NEXT: mov z0.s, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtzs s0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_sh_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: adrp x8, .LCPI64_1 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI64_1 -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: ld1rh { z1.s }, p0/z, [x8] -; CHECK-SVE-NEXT: adrp x8, .LCPI64_0 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI64_0 -; CHECK-SVE-NEXT: ld1rh { z2.s }, p0/z, [x8] -; CHECK-SVE-NEXT: fcmge p1.h, p0/z, z0.h, z1.h -; CHECK-SVE-NEXT: mov z1.s, #0x80000000 -; CHECK-SVE-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h -; CHECK-SVE-NEXT: mov z2.s, #0x7fffffff -; CHECK-SVE-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h -; CHECK-SVE-NEXT: fcvtzs z1.s, p1/m, z0.h -; CHECK-SVE-NEXT: sel z0.s, p2, z2.s, z1.s -; CHECK-SVE-NEXT: mov z0.s, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs s0, h0 ; CHECK-SVE-NEXT: ret %i = call i32 @llvm.fptosi.sat.i32.f16(half %a) %bc = bitcast i32 %i to float @@ -1984,42 +1954,12 @@ define double @fcvtzs_dh_sat_simd(half %a) { ; ; CHECK-SME-LABEL: fcvtzs_dh_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: adrp x8, .LCPI65_1 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI65_1 -; CHECK-SME-NEXT: ld1rh { z1.d }, p0/z, [x8] -; CHECK-SME-NEXT: adrp x8, .LCPI65_0 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI65_0 -; CHECK-SME-NEXT: ld1rh { z2.d }, p0/z, [x8] -; CHECK-SME-NEXT: fcmge p1.h, p0/z, z0.h, z1.h -; CHECK-SME-NEXT: mov z1.d, #0x8000000000000000 -; CHECK-SME-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h -; CHECK-SME-NEXT: mov z2.d, #0x7fffffffffffffff -; CHECK-SME-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h -; CHECK-SME-NEXT: fcvtzs z1.d, p1/m, z0.h -; CHECK-SME-NEXT: sel z0.d, p2, z2.d, z1.d -; CHECK-SME-NEXT: mov z0.d, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtzs d0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_dh_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: adrp x8, .LCPI65_1 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI65_1 -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: ld1rh { z1.d }, p0/z, [x8] -; CHECK-SVE-NEXT: adrp x8, .LCPI65_0 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI65_0 -; CHECK-SVE-NEXT: ld1rh { z2.d }, p0/z, [x8] -; CHECK-SVE-NEXT: fcmge p1.h, p0/z, z0.h, z1.h -; CHECK-SVE-NEXT: mov z1.d, #0x8000000000000000 -; CHECK-SVE-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h -; CHECK-SVE-NEXT: mov z2.d, #0x7fffffffffffffff -; CHECK-SVE-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h -; CHECK-SVE-NEXT: fcvtzs z1.d, p1/m, z0.h -; CHECK-SVE-NEXT: sel z0.d, p2, z2.d, z1.d -; CHECK-SVE-NEXT: mov z0.d, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, h0 ; CHECK-SVE-NEXT: ret %i = call i64 @llvm.fptosi.sat.i64.f16(half %a) %bc = bitcast i64 %i to double @@ -2040,38 +1980,12 @@ define double @fcvtzs_ds_sat_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzs_ds_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: mov w8, #-553648128 // =0xdf000000 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: mov z2.d, #0x8000000000000000 -; CHECK-SME-NEXT: mov z1.s, w8 -; CHECK-SME-NEXT: mov w8, #1593835519 // =0x5effffff -; CHECK-SME-NEXT: fcmge p1.s, p0/z, z0.s, z1.s -; CHECK-SME-NEXT: mov z1.s, w8 -; CHECK-SME-NEXT: fcvtzs z2.d, p1/m, z0.s -; CHECK-SME-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s -; CHECK-SME-NEXT: mov z1.d, #0x7fffffffffffffff -; CHECK-SME-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s -; CHECK-SME-NEXT: sel z0.d, p1, z1.d, z2.d -; CHECK-SME-NEXT: mov z0.d, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtzs d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_ds_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: mov w8, #-553648128 // =0xdf000000 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: mov z2.d, #0x8000000000000000 -; CHECK-SVE-NEXT: mov z1.s, w8 -; CHECK-SVE-NEXT: mov w8, #1593835519 // =0x5effffff -; CHECK-SVE-NEXT: fcmge p1.s, p0/z, z0.s, z1.s -; CHECK-SVE-NEXT: mov z1.s, w8 -; CHECK-SVE-NEXT: fcvtzs z2.d, p1/m, z0.s -; CHECK-SVE-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s -; CHECK-SVE-NEXT: mov z1.d, #0x7fffffffffffffff -; CHECK-SVE-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s -; CHECK-SVE-NEXT: sel z0.d, p1, z1.d, z2.d -; CHECK-SVE-NEXT: mov z0.d, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, s0 ; CHECK-SVE-NEXT: ret %i = call i64 @llvm.fptosi.sat.i64.f32(float %a) %bc = bitcast i64 %i to double @@ -2117,38 +2031,12 @@ define float @fcvtzs_ss_sat_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzs_ss_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: mov w8, #-822083584 // =0xcf000000 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: mov z2.s, #0x80000000 -; CHECK-SME-NEXT: mov z1.s, w8 -; CHECK-SME-NEXT: mov w8, #1325400063 // =0x4effffff -; CHECK-SME-NEXT: fcmge p1.s, p0/z, z0.s, z1.s -; CHECK-SME-NEXT: mov z1.s, w8 -; CHECK-SME-NEXT: fcvtzs z2.s, p1/m, z0.s -; CHECK-SME-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s -; CHECK-SME-NEXT: mov z1.s, #0x7fffffff -; CHECK-SME-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s -; CHECK-SME-NEXT: sel z0.s, p1, z1.s, z2.s -; CHECK-SME-NEXT: mov z0.s, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_ss_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: mov w8, #-822083584 // =0xcf000000 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: mov z2.s, #0x80000000 -; CHECK-SVE-NEXT: mov z1.s, w8 -; CHECK-SVE-NEXT: mov w8, #1325400063 // =0x4effffff -; CHECK-SVE-NEXT: fcmge p1.s, p0/z, z0.s, z1.s -; CHECK-SVE-NEXT: mov z1.s, w8 -; CHECK-SVE-NEXT: fcvtzs z2.s, p1/m, z0.s -; CHECK-SVE-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s -; CHECK-SVE-NEXT: mov z1.s, #0x7fffffff -; CHECK-SVE-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s -; CHECK-SVE-NEXT: sel z0.s, p1, z1.s, z2.s -; CHECK-SVE-NEXT: mov z0.s, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs s0, s0 ; CHECK-SVE-NEXT: ret %i = call i32 @llvm.fptosi.sat.i32.f32(float %a) %bc = bitcast i32 %i to float @@ -2168,38 +2056,12 @@ define double @fcvtzs_dd_sat_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtzs_dd_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: mov z2.d, #0x8000000000000000 -; CHECK-SME-NEXT: mov z1.d, x8 -; CHECK-SME-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff -; CHECK-SME-NEXT: fcmge p1.d, p0/z, z0.d, z1.d -; CHECK-SME-NEXT: mov z1.d, x8 -; CHECK-SME-NEXT: fcvtzs z2.d, p1/m, z0.d -; CHECK-SME-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d -; CHECK-SME-NEXT: mov z1.d, #0x7fffffffffffffff -; CHECK-SME-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d -; CHECK-SME-NEXT: sel z0.d, p1, z1.d, z2.d -; CHECK-SME-NEXT: mov z0.d, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_dd_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: mov z2.d, #0x8000000000000000 -; CHECK-SVE-NEXT: mov z1.d, x8 -; CHECK-SVE-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff -; CHECK-SVE-NEXT: fcmge p1.d, p0/z, z0.d, z1.d -; CHECK-SVE-NEXT: mov z1.d, x8 -; CHECK-SVE-NEXT: fcvtzs z2.d, p1/m, z0.d -; CHECK-SVE-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d -; CHECK-SVE-NEXT: mov z1.d, #0x7fffffffffffffff -; CHECK-SVE-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d -; CHECK-SVE-NEXT: sel z0.d, p1, z1.d, z2.d -; CHECK-SVE-NEXT: mov z0.d, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, d0 ; CHECK-SVE-NEXT: ret %i = call i64 @llvm.fptosi.sat.i64.f64(double %a) %bc = bitcast i64 %i to double @@ -2220,31 +2082,12 @@ define float @fcvtzu_sh_sat_simd(half %a) { ; ; CHECK-SME-LABEL: fcvtzu_sh_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: adrp x8, .LCPI70_0 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI70_0 -; CHECK-SME-NEXT: mov z1.s, #0 // =0x0 -; CHECK-SME-NEXT: fcmge p1.h, p0/z, z0.h, #0.0 -; CHECK-SME-NEXT: ld1rh { z2.s }, p0/z, [x8] -; CHECK-SME-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h -; CHECK-SME-NEXT: fcvtzu z1.s, p1/m, z0.h -; CHECK-SME-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff -; CHECK-SME-NEXT: fmov s0, s1 +; CHECK-SME-NEXT: fcvtzu s0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_sh_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: adrp x8, .LCPI70_0 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI70_0 -; CHECK-SVE-NEXT: mov z1.s, #0 // =0x0 -; CHECK-SVE-NEXT: fcmge p1.h, p0/z, z0.h, #0.0 -; CHECK-SVE-NEXT: ld1rh { z2.s }, p0/z, [x8] -; CHECK-SVE-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h -; CHECK-SVE-NEXT: fcvtzu z1.s, p1/m, z0.h -; CHECK-SVE-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff -; CHECK-SVE-NEXT: fmov s0, s1 +; CHECK-SVE-NEXT: fcvtzu s0, h0 ; CHECK-SVE-NEXT: ret %i = call i32 @llvm.fptoui.sat.i32.f16(half %a) %bc = bitcast i32 %i to float @@ -2265,31 +2108,12 @@ define double @fcvtzu_dh_sat_simd(half %a) { ; ; CHECK-SME-LABEL: fcvtzu_dh_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: adrp x8, .LCPI71_0 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI71_0 -; CHECK-SME-NEXT: mov z1.d, #0 // =0x0 -; CHECK-SME-NEXT: fcmge p1.h, p0/z, z0.h, #0.0 -; CHECK-SME-NEXT: ld1rh { z2.d }, p0/z, [x8] -; CHECK-SME-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h -; CHECK-SME-NEXT: fcvtzu z1.d, p1/m, z0.h -; CHECK-SME-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff -; CHECK-SME-NEXT: fmov d0, d1 +; CHECK-SME-NEXT: fcvtzu d0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_dh_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0 -; CHECK-SVE-NEXT: adrp x8, .LCPI71_0 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI71_0 -; CHECK-SVE-NEXT: mov z1.d, #0 // =0x0 -; CHECK-SVE-NEXT: fcmge p1.h, p0/z, z0.h, #0.0 -; CHECK-SVE-NEXT: ld1rh { z2.d }, p0/z, [x8] -; CHECK-SVE-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h -; CHECK-SVE-NEXT: fcvtzu z1.d, p1/m, z0.h -; CHECK-SVE-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff -; CHECK-SVE-NEXT: fmov d0, d1 +; CHECK-SVE-NEXT: fcvtzu d0, h0 ; CHECK-SVE-NEXT: ret %i = call i64 @llvm.fptoui.sat.i64.f16(half %a) %bc = bitcast i64 %i to double @@ -2310,29 +2134,12 @@ define double @fcvtzu_ds_sat_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzu_ds_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: mov w8, #1602224127 // =0x5f7fffff -; CHECK-SME-NEXT: mov z1.d, #0 // =0x0 -; CHECK-SME-NEXT: mov z2.s, w8 -; CHECK-SME-NEXT: fcmge p1.s, p0/z, z0.s, #0.0 -; CHECK-SME-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s -; CHECK-SME-NEXT: fcvtzu z1.d, p1/m, z0.s -; CHECK-SME-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff -; CHECK-SME-NEXT: fmov d0, d1 +; CHECK-SME-NEXT: fcvtzu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_ds_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: mov w8, #1602224127 // =0x5f7fffff -; CHECK-SVE-NEXT: mov z1.d, #0 // =0x0 -; CHECK-SVE-NEXT: mov z2.s, w8 -; CHECK-SVE-NEXT: fcmge p1.s, p0/z, z0.s, #0.0 -; CHECK-SVE-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s -; CHECK-SVE-NEXT: fcvtzu z1.d, p1/m, z0.s -; CHECK-SVE-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff -; CHECK-SVE-NEXT: fmov d0, d1 +; CHECK-SVE-NEXT: fcvtzu d0, s0 ; CHECK-SVE-NEXT: ret %i = call i64 @llvm.fptoui.sat.i64.f32(float %a) %bc = bitcast i64 %i to double @@ -2378,38 +2185,12 @@ define float @fcvtzu_ss_sat_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzu_ss_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: mov w8, #-822083584 // =0xcf000000 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: mov z2.s, #0x80000000 -; CHECK-SME-NEXT: mov z1.s, w8 -; CHECK-SME-NEXT: mov w8, #1325400063 // =0x4effffff -; CHECK-SME-NEXT: fcmge p1.s, p0/z, z0.s, z1.s -; CHECK-SME-NEXT: mov z1.s, w8 -; CHECK-SME-NEXT: fcvtzs z2.s, p1/m, z0.s -; CHECK-SME-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s -; CHECK-SME-NEXT: mov z1.s, #0x7fffffff -; CHECK-SME-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s -; CHECK-SME-NEXT: sel z0.s, p1, z1.s, z2.s -; CHECK-SME-NEXT: mov z0.s, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_ss_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: mov w8, #-822083584 // =0xcf000000 -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0 -; CHECK-SVE-NEXT: mov z2.s, #0x80000000 -; CHECK-SVE-NEXT: mov z1.s, w8 -; CHECK-SVE-NEXT: mov w8, #1325400063 // =0x4effffff -; CHECK-SVE-NEXT: fcmge p1.s, p0/z, z0.s, z1.s -; CHECK-SVE-NEXT: mov z1.s, w8 -; CHECK-SVE-NEXT: fcvtzs z2.s, p1/m, z0.s -; CHECK-SVE-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s -; CHECK-SVE-NEXT: mov z1.s, #0x7fffffff -; CHECK-SVE-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s -; CHECK-SVE-NEXT: sel z0.s, p1, z1.s, z2.s -; CHECK-SVE-NEXT: mov z0.s, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs s0, s0 ; CHECK-SVE-NEXT: ret %i = call i32 @llvm.fptosi.sat.i32.f32(float %a) %bc = bitcast i32 %i to float @@ -2429,38 +2210,12 @@ define double @fcvtzu_dd_sat_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtzu_dd_sat_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: mov z2.d, #0x8000000000000000 -; CHECK-SME-NEXT: mov z1.d, x8 -; CHECK-SME-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff -; CHECK-SME-NEXT: fcmge p1.d, p0/z, z0.d, z1.d -; CHECK-SME-NEXT: mov z1.d, x8 -; CHECK-SME-NEXT: fcvtzs z2.d, p1/m, z0.d -; CHECK-SME-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d -; CHECK-SME-NEXT: mov z1.d, #0x7fffffffffffffff -; CHECK-SME-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d -; CHECK-SME-NEXT: sel z0.d, p1, z1.d, z2.d -; CHECK-SME-NEXT: mov z0.d, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_dd_sat_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000 -; CHECK-SVE-NEXT: ptrue p0.d -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-SVE-NEXT: mov z2.d, #0x8000000000000000 -; CHECK-SVE-NEXT: mov z1.d, x8 -; CHECK-SVE-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff -; CHECK-SVE-NEXT: fcmge p1.d, p0/z, z0.d, z1.d -; CHECK-SVE-NEXT: mov z1.d, x8 -; CHECK-SVE-NEXT: fcvtzs z2.d, p1/m, z0.d -; CHECK-SVE-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d -; CHECK-SVE-NEXT: mov z1.d, #0x7fffffffffffffff -; CHECK-SVE-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d -; CHECK-SVE-NEXT: sel z0.d, p1, z1.d, z2.d -; CHECK-SVE-NEXT: mov z0.d, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-SVE-NEXT: fcvtzs d0, d0 ; CHECK-SVE-NEXT: ret %i = call i64 @llvm.fptosi.sat.i64.f64(double %a) %bc = bitcast i64 %i to double @@ -2485,43 +2240,12 @@ define float @fcvtas_sh_simd(half %a) { ; ; CHECK-SME-LABEL: fcvtas_sh_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: frinta h0, h0 -; CHECK-SME-NEXT: adrp x8, .LCPI76_1 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI76_1 -; CHECK-SME-NEXT: ld1rh { z1.s }, p0/z, [x8] -; CHECK-SME-NEXT: adrp x8, .LCPI76_0 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI76_0 -; CHECK-SME-NEXT: ld1rh { z2.s }, p0/z, [x8] -; CHECK-SME-NEXT: fcmge p1.h, p0/z, z0.h, z1.h -; CHECK-SME-NEXT: mov z1.s, #0x80000000 -; CHECK-SME-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h -; CHECK-SME-NEXT: mov z2.s, #0x7fffffff -; CHECK-SME-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h -; CHECK-SME-NEXT: fcvtzs z1.s, p1/m, z0.h -; CHECK-SME-NEXT: sel z0.s, p2, z2.s, z1.s -; CHECK-SME-NEXT: mov z0.s, p0/m, #0 // =0x0 +; CHECK-SME-NEXT: fcvtas s0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtas_sh_simd: ; CHECK-SVE: // %bb.0: -; CHECK-SVE-NEXT: ptrue p0.s -; CHECK-SVE-NEXT: frinta h0, h0 -; CHECK-SVE-NEXT: adrp x8, .LCPI76_1 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI76_1 -; CHECK-SVE-NEXT: ld1rh { z1.s }, p0/z, [x8] -; CHECK-SVE-NEXT: adrp x8, .LCPI76_0 -; CHECK-SVE-NEXT: add x8, x8, :lo12:.LCPI76_0 -; CHECK-SVE-NEXT: ld1rh { z2.s }, p0/z, [x8] -; CHECK-SVE-NEXT: fcmge p1.h, p0/z, z0.h, z1.h -; CHECK-SVE-NEXT: mov z1.s, #0x80000000 -; CHECK-SVE-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h -; CHECK-SVE-NEXT: mov z2.s, #0x7fffffff -; CHECK-SVE-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h -; CHECK-SVE-NEXT: fcvtzs z1.s, p1/m, z0.h -; CHECK-SVE-NEXT: sel z0.s, p2, z2.s, z1.s -; CHECK-SVE-NEXT: mov z0.s, p0/m, #0 // =0x0 -; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-SVE-NEXT: fcvtas s0, h0 ; CHECK-SVE-NEXT: ret %r = call half @llvm.round.f16(half %a) %i = call i32 @llvm.fptosi.sat.i32.f16(half %r) @@ -2543,43 +2267,12 @@ define double @fcvtas_dh_simd(half %a) { ; ; CHECK-SME-LABEL: fcvtas_dh_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: frinta h0, h0 -; CHECK-SME-NEXT: adrp x8, .LCPI77_1 -; CHECK-SME-NEXT: add x8, x8, :lo12:.LCPI77_1 -; CHECK-SME-NEXT: ld1rh { z1.d }, p0/z, [x8] -; CHECK-SME-NEXT: adrp x8, .LCPI77_0 -; CHECK-SME-NEXT: ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/180932 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
