https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/195773
Backport 475cc4fe0b4065775db470bb512c9c9142242e55 Requested by: @amy-kwan >From 7d9db980d2b57738d152986acc3174f6ec9cd259 Mon Sep 17 00:00:00 2001 From: Florian Hahn <[email protected]> Date: Thu, 12 Mar 2026 21:51:23 +0000 Subject: [PATCH] [VPlan] Account for any-of costs in legacy cost model Some VPlan transforms, like vectorizing fmin without fast-math, introduce AnyOfs, which have costs assigned in the VPlan-based cost model, but not the legacy cost model. Account for their cost like done for other similar VPInstrctions, like EVL. Fixes https://github.com/llvm/llvm-project/issues/185867. (cherry picked from commit 475cc4fe0b4065775db470bb512c9c9142242e55) --- .../Transforms/Vectorize/LoopVectorize.cpp | 1 + .../LoopVectorize/X86/cost-any-of.ll | 84 +++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/X86/cost-any-of.ll diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index cdc6ecfa21bcb..77589e06d9c33 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -4282,6 +4282,7 @@ VectorizationFactor LoopVectorizationPlanner::selectVectorizationFactor() { break; } case VPInstruction::ExplicitVectorLength: + case VPInstruction::AnyOf: C += VPI->cost(VF, CostCtx); break; default: diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-any-of.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-any-of.ll new file mode 100644 index 0000000000000..eab48211bf8d8 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/X86/cost-any-of.ll @@ -0,0 +1,84 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 +; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s + +target triple = "x86_64-unknown-linux-gnu" + +; Test case for https://github.com/llvm/llvm-project/issues/185867. +define void @fminnum_with_any_of_cost(ptr %p) #0 { +; CHECK-LABEL: define void @fminnum_with_any_of_cost( +; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: br label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <16 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <16 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <16 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds float, ptr [[P]], i64 [[INDEX]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i64 16 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i64 32 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i64 48 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x float>, ptr [[TMP0]], align 4 +; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x float>, ptr [[TMP1]], align 4 +; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <16 x float>, ptr [[TMP2]], align 4 +; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <16 x float>, ptr [[TMP3]], align 4 +; CHECK-NEXT: [[TMP4]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[VEC_PHI]], <16 x float> [[WIDE_LOAD]]) +; CHECK-NEXT: [[TMP5]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[VEC_PHI1]], <16 x float> [[WIDE_LOAD4]]) +; CHECK-NEXT: [[TMP6]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[VEC_PHI2]], <16 x float> [[WIDE_LOAD5]]) +; CHECK-NEXT: [[TMP7]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[VEC_PHI3]], <16 x float> [[WIDE_LOAD6]]) +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64 +; CHECK-NEXT: [[TMP8:%.*]] = fcmp uno <16 x float> [[WIDE_LOAD]], [[WIDE_LOAD4]] +; CHECK-NEXT: [[TMP9:%.*]] = fcmp uno <16 x float> [[WIDE_LOAD5]], [[WIDE_LOAD6]] +; CHECK-NEXT: [[TMP10:%.*]] = freeze <16 x i1> [[TMP8]] +; CHECK-NEXT: [[TMP11:%.*]] = freeze <16 x i1> [[TMP9]] +; CHECK-NEXT: [[TMP12:%.*]] = or <16 x i1> [[TMP10]], [[TMP11]] +; CHECK-NEXT: [[TMP13:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP12]]) +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128 +; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP13]], [[TMP14]] +; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP13]], <16 x float> [[VEC_PHI]], <16 x float> [[TMP4]] +; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP13]], <16 x float> [[VEC_PHI1]], <16 x float> [[TMP5]] +; CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP13]], <16 x float> [[VEC_PHI2]], <16 x float> [[TMP6]] +; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP13]], <16 x float> [[VEC_PHI3]], <16 x float> [[TMP7]] +; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP13]], i64 [[INDEX]], i64 128 +; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[TMP16]], <16 x float> [[TMP17]]) +; CHECK-NEXT: [[RDX_MINMAX7:%.*]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[RDX_MINMAX]], <16 x float> [[TMP18]]) +; CHECK-NEXT: [[RDX_MINMAX8:%.*]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[RDX_MINMAX7]], <16 x float> [[TMP19]]) +; CHECK-NEXT: [[TMP21:%.*]] = call float @llvm.vector.reduce.fmin.v16f32(<16 x float> [[RDX_MINMAX8]]) +; CHECK-NEXT: br label %[[SCALAR_PH:.*]] +; CHECK: [[SCALAR_PH]]: +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[TMP20]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[RED:%.*]] = phi float [ [[TMP21]], %[[SCALAR_PH]] ], [ [[MIN:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr [[P]], i64 [[IV]] +; CHECK-NEXT: [[LDV:%.*]] = load float, ptr [[GEP]], align 4 +; CHECK-NEXT: [[MIN]] = tail call float @llvm.minnum.f32(float [[RED]], float [[LDV]]) +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 140 +; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %red = phi float [ 0.000000e+00, %entry ], [ %min, %loop ] + %gep = getelementptr inbounds float, ptr %p, i64 %iv + %ldv = load float, ptr %gep, align 4 + %min = tail call float @llvm.minnum.f32(float %red, float %ldv) + %iv.next = add i64 %iv, 1 + %cmp = icmp eq i64 %iv.next, 140 + br i1 %cmp, label %exit, label %loop + +exit: + ret void +} + +attributes #0 = { "target-cpu"="znver4" } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
