https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/194811
>From 4149f70b9126274f10058144d3b14f0d312b5a12 Mon Sep 17 00:00:00 2001 From: Aaditya <[email protected]> Date: Tue, 28 Apr 2026 14:35:01 +0530 Subject: [PATCH] [AMDGPU] Support Wave Reduction for true-16 types - 2 Supporting true-16 versions of the reduction intrinsics Supported Ops: `add`, `sub`. Supports only the iterative stratergy, DPP is yet to be supported. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 + llvm/lib/Target/AMDGPU/SIInstructions.td | 4 +- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll | 535 +++++++++++------ .../CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll | 560 ++++++++++++------ 4 files changed, 741 insertions(+), 364 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 37e374646a8e6..09211dd31fb84 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5687,6 +5687,8 @@ static bool is16bitWaveReduction(unsigned Opc) { Opc == AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I16_t16 || Opc == AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I16 || Opc == AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I16 || + Opc == AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I16_t16 || + Opc == AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I16_t16 || Opc == AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I16; } @@ -6069,7 +6071,9 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, MI.getOpcode() == AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I16 || MI.getOpcode() == AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I16_t16 || MI.getOpcode() == AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I16 || + MI.getOpcode() == AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I16_t16 || MI.getOpcode() == AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I16 || + MI.getOpcode() == AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I16_t16 || MI.getOpcode() == AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I16; bool useRealTrue16 = ST.useRealTrue16Insts(); // Create virtual registers required for lowering. @@ -6770,6 +6774,7 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, ST.getGeneration() >= AMDGPUSubtarget::GFX12 ? AMDGPU::V_MAX_NUM_F64_e64 : AMDGPU::V_MAX_F64_e64); + case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I16_t16: case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I16: case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I32: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_ADD_I32); @@ -6782,6 +6787,7 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, ST.getGeneration() >= AMDGPUSubtarget::GFX12 ? AMDGPU::V_ADD_F64_pseudo_e64 : AMDGPU::V_ADD_F64_e64); + case AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I16_t16: case AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I16: case AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I32: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_SUB_I32); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index f54e01a6b8656..1afcb3ecc38ba 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -417,7 +417,9 @@ defvar Operations = [ WaveReduceOp<"umin", "U16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, WaveReduceOp<"min", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, WaveReduceOp<"umax", "U16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, - WaveReduceOp<"max", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts> + WaveReduceOp<"max", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, + WaveReduceOp<"add", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, + WaveReduceOp<"sub", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts> ]; foreach Op = Operations in { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll index 67a0248b11903..d56cd31cf7a0e 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll @@ -7,11 +7,16 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL,GFX12DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL,GFX12DAGISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -128,78 +133,153 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v1, v0, s[0:1] ; GFX1032GISEL-NEXT: s_endpgm ; -; GFX1164DAGISEL-LABEL: uniform_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_clause 0x1 -; GFX1164DAGISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c -; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1164DAGISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3] -; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164DAGISEL-NEXT: s_mul_i32 s2, s6, s2 -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1164DAGISEL-NEXT: s_endpgm -; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3] -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s3, 0xffff, s6 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm -; -; GFX1132DAGISEL-LABEL: uniform_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_clause 0x1 -; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132DAGISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 -; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1132DAGISEL-NEXT: s_endpgm -; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm -; -; GFX12DAGISEL-LABEL: uniform_value_i16: -; GFX12DAGISEL: ; %bb.0: ; %entry -; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 -; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX12DAGISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12DAGISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 -; GFX12DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX12DAGISEL-NEXT: s_endpgm +; GFX1164DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s6, s2 +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s3, 0xffff, s6 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1132DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX12DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX12DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX12DAGISEL-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 +; GFX12DAGISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX12DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX12DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX12DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX12DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX12DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s6, s2 +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s3, 0xffff, s6 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm +; +; GFX12DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX12DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX12DAGISEL-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 +; GFX12DAGISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX12DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX12DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX12DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX12DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX12DAGISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.add.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -355,106 +435,207 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_add_i32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1164GISEL-LABEL: divergent_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164GISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164GISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164GISEL-NEXT: s_add_i32 s2, s2, s4 -; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164GISEL-NEXT: ; %bb.2: -; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_add_i32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132GISEL-LABEL: divergent_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132GISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132GISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132GISEL-NEXT: s_add_i32 s0, s0, s3 -; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132GISEL-NEXT: ; %bb.2: -; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX12DAGISEL-LABEL: divergent_value_i16: -; GFX12DAGISEL: ; %bb.0: ; %entry -; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX12DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX12DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX12DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX12DAGISEL-NEXT: s_add_co_i32 s0, s0, s3 -; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX12DAGISEL-NEXT: ; %bb.2: -; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX12DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_add_i32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-FAKE16-NEXT: s_add_i32 s2, s2, s4 +; GFX1164GISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_add_i32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-FAKE16-NEXT: s_add_i32 s0, s0, s3 +; GFX1132GISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX12DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX12DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX12DAGISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_expcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_samplecnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX12DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX12DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX12DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX12DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX12DAGISEL-FAKE16-NEXT: s_add_co_i32 s0, s0, s3 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX12DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX12DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX12DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX12DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX12DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_add_i32 s2, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-TRUE16-NEXT: s_add_i32 s2, s2, s4 +; GFX1164GISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_add_i32 s0, s0, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s0 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1132GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-TRUE16-NEXT: s_add_i32 s0, s0, s3 +; GFX1132GISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s0 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX12DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX12DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX12DAGISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_expcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_samplecnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX12DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX12DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX12DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX12DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX12DAGISEL-TRUE16-NEXT: s_add_co_i32 s0, s0, s3 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX12DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX12DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX12DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s0 +; GFX12DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX12DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.add.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll index c77be80105625..d596545648fdc 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll @@ -7,11 +7,16 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s -; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=-real-true16 -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL,GFX12DAGISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mattr=+real-true16 -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL,GFX12DAGISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -136,87 +141,169 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v1, v0, s[0:1] ; GFX1032GISEL-NEXT: s_endpgm ; -; GFX1164DAGISEL-LABEL: uniform_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_clause 0x1 -; GFX1164DAGISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c -; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1164DAGISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3] -; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164DAGISEL-NEXT: s_sub_i32 s3, 0, s6 -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: s_mul_i32 s2, s3, s2 -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1164DAGISEL-NEXT: s_endpgm -; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3] -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s4, 0xffff, s6 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: s_sub_i32 s3, 0, s4 -; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm -; -; GFX1132DAGISEL-LABEL: uniform_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_clause 0x1 -; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132DAGISEL-NEXT: s_sub_i32 s2, 0, s2 -; GFX1132DAGISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 -; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1132DAGISEL-NEXT: s_endpgm -; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: s_sub_i32 s2, 0, s2 -; GFX1132GISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm -; -; GFX12DAGISEL-LABEL: uniform_value_i16: -; GFX12DAGISEL: ; %bb.0: ; %entry -; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 -; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX12DAGISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12DAGISEL-NEXT: s_sub_co_i32 s2, 0, s2 -; GFX12DAGISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 -; GFX12DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX12DAGISEL-NEXT: s_endpgm +; GFX1164DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: s_sub_i32 s3, 0, s6 +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s4, 0xffff, s6 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: s_sub_i32 s3, 0, s4 +; GFX1164GISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: s_sub_i32 s2, 0, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1132DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: s_sub_i32 s2, 0, s2 +; GFX1132GISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX12DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX12DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX12DAGISEL-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 +; GFX12DAGISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX12DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX12DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_sub_co_i32 s2, 0, s2 +; GFX12DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX12DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX12DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX12DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: s_sub_i32 s3, 0, s6 +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s4, 0xffff, s6 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: s_sub_i32 s3, 0, s4 +; GFX1164GISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: s_sub_i32 s2, 0, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: s_sub_i32 s2, 0, s2 +; GFX1132GISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm +; +; GFX12DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX12DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX12DAGISEL-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 +; GFX12DAGISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX12DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX12DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_sub_co_i32 s2, 0, s2 +; GFX12DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX12DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX12DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX12DAGISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.sub.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -372,106 +459,207 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_sub_i32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1164GISEL-LABEL: divergent_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164GISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164GISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164GISEL-NEXT: s_sub_i32 s2, s2, s4 -; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164GISEL-NEXT: ; %bb.2: -; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_sub_i32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132GISEL-LABEL: divergent_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132GISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132GISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132GISEL-NEXT: s_sub_i32 s0, s0, s3 -; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132GISEL-NEXT: ; %bb.2: -; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX12DAGISEL-LABEL: divergent_value_i16: -; GFX12DAGISEL: ; %bb.0: ; %entry -; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0 -; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16 -; GFX12DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX12DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX12DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX12DAGISEL-NEXT: s_sub_co_i32 s0, s0, s3 -; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) -; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX12DAGISEL-NEXT: ; %bb.2: -; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX12DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_sub_i32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-FAKE16-NEXT: s_sub_i32 s2, s2, s4 +; GFX1164GISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_sub_i32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-FAKE16-NEXT: s_sub_i32 s0, s0, s3 +; GFX1132GISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX12DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX12DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX12DAGISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_expcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_samplecnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX12DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX12DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX12DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX12DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX12DAGISEL-FAKE16-NEXT: s_sub_co_i32 s0, s0, s3 +; GFX12DAGISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX12DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX12DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX12DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX12DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX12DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_sub_i32 s2, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-TRUE16-NEXT: s_sub_i32 s2, s2, s4 +; GFX1164GISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_sub_i32 s0, s0, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s0 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1132GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-TRUE16-NEXT: s_sub_i32 s0, s0, s3 +; GFX1132GISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s0 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX12DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX12DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX12DAGISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_expcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_samplecnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX12DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX12DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo +; GFX12DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX12DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX12DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2 +; GFX12DAGISEL-TRUE16-NEXT: s_sub_co_i32 s0, s0, s3 +; GFX12DAGISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX12DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX12DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX12DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s0 +; GFX12DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX12DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.sub.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
