================
@@ -471,6 +493,73 @@ LaneBitmask llvm::getLiveLaneMask(unsigned Reg, SlotIndex
SI,
return getLiveLaneMask(LIS.getInterval(Reg), SI, MRI, LaneMaskFilter);
}
+bool GCNRPTracker::isUnitLiveAt(MCRegUnit Unit, SlotIndex SI) const {
+ const LiveRange *LR = LIS.getCachedRegUnit(Unit);
+ // If LIS has no reg-unit live range, be conservative and assume it is live.
+ return !LR || LR->liveAt(SI);
+}
+
+bool GCNRPTracker::isAnyRegUnitNotLive(MCRegister Reg) const {
+ assert(SRI && "SRI not initialized");
+ const BitVector &Units = PhysLiveRegs.getBitVector();
+ return llvm::any_of(SRI->regunits(Reg), [&](MCRegUnit Unit) {
+ return !Units.test(static_cast<unsigned>(Unit));
+ });
+}
+
+bool GCNRPTracker::checkRegKilled(MCRegister Reg, SlotIndex SI) const {
+ assert(SRI && "SRI not initialized");
+ const BitVector &Units = PhysLiveRegs.getBitVector();
+ return llvm::any_of(SRI->regunits(Reg), [&](MCRegUnit Unit) {
+ return Units.test(static_cast<unsigned>(Unit)) && !isUnitLiveAt(Unit, SI);
+ });
+}
+
+bool GCNRPTracker::eraseKilledUnits(MCRegister Reg, SlotIndex SI) {
+ assert(SRI && "SRI not initialized");
+ // Due to aliasing, a physical register may not be present in
+ // PhysLiveRegs.Regs, but one of its regunits may show up as killed. Return
+ // early in this case.
+ if (!PhysLiveRegs.Regs.contains(Reg))
+ return false;
+ BitVector KilledUnits(PhysLiveRegs.getBitVector().size(), false);
+ for (MCRegUnit Unit : SRI->regunits(Reg)) {
+ unsigned U = static_cast<unsigned>(Unit);
+ if (PhysLiveRegs.getBitVector().test(U) && !isUnitLiveAt(Unit, SI))
+ KilledUnits.set(U);
+ }
+ if (KilledUnits.none())
+ return false;
+ PhysLiveRegs.remove(KilledUnits, Reg);
+ return true;
+}
+
+bool GCNRPTracker::eraseAllLiveUnits(MCRegister Reg) {
+ assert(SRI && "SRI not initialized");
+ if (!PhysLiveRegs.Regs.contains(Reg))
+ return false;
+ PhysLiveRegs.remove(Reg);
+ return true;
+}
+
+bool GCNRPTracker::insertIfNotLive(MCRegister Reg) {
+ assert(SRI && "SRI not initialized");
+ const BitVector &Units = PhysLiveRegs.getBitVector();
+ bool NewlyLive = llvm::any_of(SRI->regunits(Reg), [&](MCRegUnit Unit) {
+ return !Units.test(static_cast<unsigned>(Unit));
+ });
----------------
macurtis-amd wrote:
replace with `bool NewlyLive = isAnyRegUnitNotLive(Reg);`?
https://github.com/llvm/llvm-project/pull/184275
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