================
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 6
+; RUN: llc -O2 -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 \
+; RUN: -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck %s \
+; RUN: --check-prefix=COMBINE --implicit-check-not=REG_SEQUENCE
+; RUN: llc -O2 -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 \
+; RUN: -verify-machineinstrs -combiner-disabled -stop-after=amdgpu-isel < %s
\
+; RUN: | FileCheck %s --check-prefix=NOCOMBINE
+
+declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64 immarg)
+declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64 immarg)
+
+define <2 x i32> @extract_of_extract_nonzero(<8 x i32> %x) nounwind {
+ ; COMBINE-LABEL: name: extract_of_extract_nonzero
+ ; COMBINE: bb.0 (%ir-block.0):
+ ; COMBINE-NEXT: liveins: $vgpr6, $vgpr7
+ ; COMBINE-NEXT: {{ $}}
+ ; COMBINE-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr7
+ ; COMBINE-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr6
+ ; COMBINE-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; COMBINE-NEXT: $vgpr1 = COPY [[COPY]]
+ ; COMBINE-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
+ ;
+ ; NOCOMBINE-LABEL: name: extract_of_extract_nonzero
+ ; NOCOMBINE: bb.0 (%ir-block.0):
+ ; NOCOMBINE-NEXT: liveins: $vgpr4, $vgpr5, $vgpr6, $vgpr7
+ ; NOCOMBINE-NEXT: {{ $}}
+ ; NOCOMBINE-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr7
+ ; NOCOMBINE-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr6
+ ; NOCOMBINE-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr5
+ ; NOCOMBINE-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr4
+ ; NOCOMBINE-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE
[[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY1]], %subreg.sub2,
[[COPY]], %subreg.sub3
+ ; NOCOMBINE-NEXT: [[COPY4:%[0-9]+]]:av_32 = COPY [[REG_SEQUENCE]].sub3
+ ; NOCOMBINE-NEXT: [[COPY5:%[0-9]+]]:av_32 = COPY [[REG_SEQUENCE]].sub2
+ ; NOCOMBINE-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:av_64_align2 = REG_SEQUENCE
killed [[COPY5]], %subreg.sub0, killed [[COPY4]], %subreg.sub1
+ ; NOCOMBINE-NEXT: [[COPY6:%[0-9]+]]:av_32 = COPY [[REG_SEQUENCE1]].sub0
+ ; NOCOMBINE-NEXT: [[COPY7:%[0-9]+]]:av_32 = COPY [[REG_SEQUENCE1]].sub1
+ ; NOCOMBINE-NEXT: $vgpr0 = COPY [[COPY6]]
+ ; NOCOMBINE-NEXT: $vgpr1 = COPY [[COPY7]]
+ ; NOCOMBINE-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
+ %mid = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %x, i64 4)
+ %out = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %mid, i64 2)
+ ret <2 x i32> %out
+}
----------------
RKSimon wrote:
why bother with the nocombine? why not just a basic ir llc test?
https://github.com/llvm/llvm-project/pull/200935
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