https://github.com/krzysz00 updated https://github.com/llvm/llvm-project/pull/200933
>From 8c5f91f1f259a8b0b441e7865f9acdc2d6107a97 Mon Sep 17 00:00:00 2001 From: Krzysztof Drewniak <[email protected]> Date: Fri, 29 May 2026 22:30:39 +0000 Subject: [PATCH] [SelectionDAG] Track bitcast demanded elements in noundef tests Bitcasts preserve undef/poison status, but vector bitcasts can change which source lanes cover a demanded result lane. Map the demanded element mask through fixed-length vector bitcasts before checking the source where possible. AI note: an LLM generated the code and the test, I've read them Co-Authored-By: OpenAI Codex <[email protected]> --- .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 41 +++++++++++++++++++ ...dagcombine-freeze-bitcast-demanded-elts.ll | 5 +-- 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 057b3df5a4627..eba9327c83cd4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5654,6 +5654,47 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::UNDEF: return !includesUndef(Kind); + case ISD::BITCAST: { + if (!DemandedElts) + return true; + + SDValue Src = Op.getOperand(0); + EVT SrcVT = Src.getValueType(); + EVT DstVT = Op.getValueType(); + + if (!SrcVT.isFixedLengthVector() || !DstVT.isFixedLengthVector()) + return isGuaranteedNotToBeUndefOrPoison(Src, Kind, Depth + 1); + + unsigned SrcEltBits = SrcVT.getScalarSizeInBits(); + unsigned DstEltBits = DstVT.getScalarSizeInBits(); + unsigned NumSrcElts = SrcVT.getVectorNumElements(); + unsigned NumDstElts = DstVT.getVectorNumElements(); + + if (SrcEltBits == DstEltBits) + return isGuaranteedNotToBeUndefOrPoison(Src, DemandedElts, Kind, + Depth + 1); + + if (SrcEltBits < DstEltBits) { + if (DstEltBits % SrcEltBits != 0) + return isGuaranteedNotToBeUndefOrPoison(Src, Kind, Depth + 1); + + assert(NumSrcElts == NumDstElts * (DstEltBits / SrcEltBits) && + "Unexpected fixed-width vector bitcast"); + APInt DemandedSrcElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts); + return isGuaranteedNotToBeUndefOrPoison(Src, DemandedSrcElts, Kind, + Depth + 1); + } + + if (SrcEltBits % DstEltBits != 0) + return isGuaranteedNotToBeUndefOrPoison(Src, Kind, Depth + 1); + + assert(NumDstElts == NumSrcElts * (SrcEltBits / DstEltBits) && + "Unexpected fixed-width vector bitcast"); + APInt DemandedSrcElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts); + return isGuaranteedNotToBeUndefOrPoison(Src, DemandedSrcElts, Kind, + Depth + 1); + } + case ISD::BUILD_VECTOR: // NOTE: BUILD_VECTOR has implicit truncation of wider scalar elements - // this shouldn't affect the result. diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll index 16fdc7fb7d6de..60b14a7068141 100644 --- a/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll +++ b/llvm/test/CodeGen/X86/dagcombine-freeze-bitcast-demanded-elts.ll @@ -6,10 +6,7 @@ declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64 immarg) define <4 x i32> @freeze_extract_bitcast_high_demanded(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: freeze_extract_bitcast_high_demanded: ; CHECK: # %bb.0: -; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 -; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0 -; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0 -; CHECK-NEXT: vzeroupper +; CHECK-NEXT: vpsrld $1, %xmm1, %xmm0 ; CHECK-NEXT: retq %poisonable = add nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> %wide = shufflevector <2 x i64> %poisonable, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3> _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
