https://github.com/krzysz00 updated https://github.com/llvm/llvm-project/pull/200934
>From 9fbcc6cc360a09f717137921b4e657155223d8b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Drewniak <[email protected]> Date: Fri, 29 May 2026 22:35:59 +0000 Subject: [PATCH] [SelectionDAG] Track demanded select elements in noundef checks Propagate demanded elements through to the two arms of a select, and check the condition with or without demanded elements depending on if it's a vector or not. AI note: an LLM generated the code and the test, I've read them Co-Authored-By: OpenAI Codex <[email protected]> --- .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 19 +++++++++++++++++-- .../dagcombine-freeze-select-demanded-elts.ll | 10 ---------- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index eba9327c83cd4..7e274a8f8d9c2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5810,6 +5810,22 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::SPLAT_VECTOR: return isGuaranteedNotToBeUndefOrPoison(Op.getOperand(0), Kind, Depth + 1); + case ISD::SELECT: + case ISD::VSELECT: { + SDValue Cond = Op.getOperand(0); + bool CondIsVector = Cond.getValueType().isVector(); + return !canCreateUndefOrPoison(Op, DemandedElts, Kind, + /*ConsiderFlags*/ true, Depth) && + (CondIsVector + ? isGuaranteedNotToBeUndefOrPoison(Cond, DemandedElts, Kind, + Depth + 1) + : isGuaranteedNotToBeUndefOrPoison(Cond, Kind, Depth + 1)) && + isGuaranteedNotToBeUndefOrPoison(Op.getOperand(1), DemandedElts, + Kind, Depth + 1) && + isGuaranteedNotToBeUndefOrPoison(Op.getOperand(2), DemandedElts, + Kind, Depth + 1); + } + case ISD::VECTOR_SHUFFLE: { APInt DemandedLHS, DemandedRHS; auto *SVN = cast<ShuffleVectorSDNode>(Op); @@ -5860,8 +5876,7 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND: case ISD::ANY_EXTEND: - case ISD::TRUNCATE: - case ISD::VSELECT: { + case ISD::TRUNCATE: { // If Op can't create undef/poison and none of its operands are undef/poison // then Op is never undef/poison. A difference from the more common check // below, outside the switch, is that we handle elementwise operations for diff --git a/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll b/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll index 21241af18a3c9..d768b39bbd4c3 100644 --- a/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll +++ b/llvm/test/CodeGen/X86/dagcombine-freeze-select-demanded-elts.ll @@ -6,16 +6,6 @@ declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64 immarg) define i32 @freeze_select_scalar_demanded(i1 %c, <2 x i32> %a, <2 x i32> %b, <2 x i32> %d) { ; CHECK-LABEL: freeze_select_scalar_demanded: ; CHECK: # %bb.0: -; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: -; CHECK-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 -; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] -; CHECK-NEXT: movd %xmm0, %eax -; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: -; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [2147483647,2147483647,u,u] -; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: retq %poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647> _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
