Author: Jay Foad Date: 2026-06-17T19:44:17+01:00 New Revision: 0eb257578697efd4ac05f1cf1f9d0c5c4ef5d53f
URL: https://github.com/llvm/llvm-project/commit/0eb257578697efd4ac05f1cf1f9d0c5c4ef5d53f DIFF: https://github.com/llvm/llvm-project/commit/0eb257578697efd4ac05f1cf1f9d0c5c4ef5d53f.diff LOG: [CodeGen] Pass the correct VT into hasMultipleConditionRegisters (#204375) hasMultipleConditionRegisters expects the type of the condition value. Fix shouldNormalizeToSelectSequence to pass this in instead of the type of the result of a select. In practice this makes no observable difference yet. AArch64 is the only target that uses the VT passed into hasMultipleConditionRegisters and it only checks whether or not it is a scalable vector type. Added: Modified: llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h llvm/lib/Target/RISCV/RISCVISelLowering.h Removed: ################################################################################ diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index a44c0a5a8bc23..7a10a693934fd 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -527,7 +527,8 @@ class LLVM_ABI TargetLoweringBase { /// can be used to store the results of comparisons for use by selects /// and conditional branches. With multiple condition registers, the code /// generator will not aggressively sink comparisons into the blocks of their - /// users. + /// users. \p VT is the type of the condition value, e.g. the type of the + /// result of a comparison. virtual bool hasMultipleConditionRegisters(EVT VT) const { return false; } /// Return true if the target has BitExtract instructions. @@ -2550,8 +2551,10 @@ class LLVM_ABI TargetLoweringBase { /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely /// that it saves us from materializing N0 and N1 in an integer register. /// Targets that are able to perform and/or on flags should return false here. - virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, - EVT VT) const { + /// \p VT is the type of the select (and X and Y). \p CCVT is the type of its + /// condition (N0 and N1). + virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT, + EVT CCVT) const { // If a target has multiple condition registers, then it likely has logical // operations on those registers. if (hasMultipleConditionRegisters(VT)) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7fdaacff0582d..5a4ae64cb98af 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -13076,7 +13076,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { // and we always transform to the left side if we know that we can further // optimize the combination of the conditions. bool normalizeToSequence = - TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT); + TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT, VT0); // select (and Cond0, Cond1), X, Y // -> select Cond0, (select Cond1, X, Y), Y if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) { diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index fc1640a8bd199..67ef911117eff 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -31646,7 +31646,7 @@ bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters( return all_equal(ValueVTs); } -bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &, +bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &, EVT, EVT) const { return false; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 5c3e2e09d596c..704eed7877bdc 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -906,7 +906,7 @@ class AArch64TargetLowering : public TargetLowering { SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const; - bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override; + bool shouldNormalizeToSelectSequence(LLVMContext &, EVT, EVT) const override; void finalizeLowering(MachineFunction &MF) const override; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index c1d31c944714c..4e7912ed815dd 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -610,7 +610,7 @@ class RISCVTargetLowering : public TargetLowering { /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR. - bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override { + bool shouldNormalizeToSelectSequence(LLVMContext &, EVT, EVT) const override { return false; } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
