Author: Nikita Popov Date: 2026-06-24T17:48:47+02:00 New Revision: d0d14c6388058c809e91963e9892c7f1499765ac
URL: https://github.com/llvm/llvm-project/commit/d0d14c6388058c809e91963e9892c7f1499765ac DIFF: https://github.com/llvm/llvm-project/commit/d0d14c6388058c809e91963e9892c7f1499765ac.diff LOG: Revert "[AArch64] Run cleanup one final time after peephole (#199711)" This reverts commit 448c3d54df7bcd5e5be2b5d051832ad00b4cc89c. Added: Modified: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp llvm/test/CodeGen/AArch64/O3-pipeline.ll llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll llvm/test/CodeGen/AArch64/fabs-fp128.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index c20fb31ab8854..568563cf53220 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -815,10 +815,8 @@ void AArch64PassConfig::addMachineSSAOptimization() { // Run default MachineSSAOptimization first. TargetPassConfig::addMachineSSAOptimization(); - if (TM->getOptLevel() != CodeGenOptLevel::None) { + if (TM->getOptLevel() != CodeGenOptLevel::None) addPass(createAArch64MIPeepholeOptLegacyPass()); - addPass(&DeadMachineInstructionElimID); - } } bool AArch64PassConfig::addILPOpts() { diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll index ed2453941866a..08d3b94530d14 100644 --- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll +++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll @@ -172,7 +172,6 @@ ; CHECK-NEXT: Peephole Optimizations ; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: AArch64 MI Peephole Optimization pass -; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: AArch64 Dead register definitions ; CHECK-NEXT: Detect Dead Lanes ; CHECK-NEXT: Init Undef Pass diff --git a/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll b/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll index 72270e3be443f..91eda8d552397 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll @@ -210,9 +210,9 @@ define void @insert_vec_v8i16_uaddlv_from_v8i16(ptr %0) { ; CHECK-NEXT: stp xzr, xzr, [x0, #16] ; CHECK-NEXT: uaddlv.8h s0, v0 ; CHECK-NEXT: mov.h v1[0], v0[0] -; CHECK-NEXT: ushll.4s v0, v1, #0 -; CHECK-NEXT: ucvtf.4s v0, v0 -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ushll.4s v1, v1, #0 +; CHECK-NEXT: ucvtf.4s v1, v1 +; CHECK-NEXT: str q1, [x0] ; CHECK-NEXT: ret entry: @@ -232,10 +232,10 @@ define void @insert_vec_v3i16_uaddlv_from_v8i16(ptr %0) { ; CHECK-NEXT: add x8, x0, #8 ; CHECK-NEXT: uaddlv.8h s0, v0 ; CHECK-NEXT: mov.h v1[0], v0[0] -; CHECK-NEXT: ushll.4s v0, v1, #0 -; CHECK-NEXT: ucvtf.4s v0, v0 -; CHECK-NEXT: st1.s { v0 }[2], [x8] -; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ushll.4s v1, v1, #0 +; CHECK-NEXT: ucvtf.4s v1, v1 +; CHECK-NEXT: st1.s { v1 }[2], [x8] +; CHECK-NEXT: str d1, [x0] ; CHECK-NEXT: ret entry: @@ -283,9 +283,9 @@ define void @insert_vec_v16i8_uaddlv_from_v8i8(ptr %0) { ; CHECK-NEXT: stp q0, q0, [x0, #32] ; CHECK-NEXT: mov.h v2[0], v1[0] ; CHECK-NEXT: bic.4h v2, #255, lsl #8 -; CHECK-NEXT: ushll.4s v1, v2, #0 -; CHECK-NEXT: ucvtf.4s v1, v1 -; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: ushll.4s v2, v2, #0 +; CHECK-NEXT: ucvtf.4s v2, v2 +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret entry: @@ -389,9 +389,9 @@ define void @insert_vec_v4i16_uaddlv_from_v4i32(ptr %0) { ; CHECK-NEXT: movi.2d v1, #0000000000000000 ; CHECK-NEXT: uaddlv.4s d0, v0 ; CHECK-NEXT: mov.h v1[0], v0[0] -; CHECK-NEXT: ushll.4s v0, v1, #0 -; CHECK-NEXT: ucvtf.4s v0, v0 -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ushll.4s v1, v1, #0 +; CHECK-NEXT: ucvtf.4s v1, v1 +; CHECK-NEXT: str q1, [x0] ; CHECK-NEXT: ret entry: @@ -408,13 +408,13 @@ define void @insert_vec_v16i16_uaddlv_from_v4i32(ptr %0) { ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: movi.2d v0, #0000000000000000 ; CHECK-NEXT: movi.2d v1, #0000000000000000 +; CHECK-NEXT: movi.2d v2, #0000000000000000 ; CHECK-NEXT: uaddlv.4s d0, v0 +; CHECK-NEXT: stp q2, q2, [x0, #32] ; CHECK-NEXT: mov.h v1[0], v0[0] -; CHECK-NEXT: movi.2d v0, #0000000000000000 ; CHECK-NEXT: ushll.4s v1, v1, #0 -; CHECK-NEXT: stp q0, q0, [x0, #32] ; CHECK-NEXT: ucvtf.4s v1, v1 -; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: stp q1, q2, [x0] ; CHECK-NEXT: ret entry: @@ -435,9 +435,9 @@ define void @insert_vec_v8i8_uaddlv_from_v4i32(ptr %0) { ; CHECK-NEXT: uaddlv.4s d0, v0 ; CHECK-NEXT: mov.h v1[0], v0[0] ; CHECK-NEXT: bic.4h v1, #255, lsl #8 -; CHECK-NEXT: ushll.4s v0, v1, #0 -; CHECK-NEXT: ucvtf.4s v0, v0 -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ushll.4s v1, v1, #0 +; CHECK-NEXT: ucvtf.4s v1, v1 +; CHECK-NEXT: str q1, [x0] ; CHECK-NEXT: ret entry: @@ -454,14 +454,14 @@ define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) { ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: movi.2d v0, #0000000000000000 ; CHECK-NEXT: movi.2d v1, #0000000000000000 +; CHECK-NEXT: movi.2d v2, #0000000000000000 ; CHECK-NEXT: uaddlv.4s d0, v0 +; CHECK-NEXT: stp q2, q2, [x0, #32] ; CHECK-NEXT: mov.h v1[0], v0[0] -; CHECK-NEXT: movi.2d v0, #0000000000000000 ; CHECK-NEXT: bic.4h v1, #255, lsl #8 -; CHECK-NEXT: stp q0, q0, [x0, #32] ; CHECK-NEXT: ushll.4s v1, v1, #0 ; CHECK-NEXT: ucvtf.4s v1, v1 -; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: stp q1, q2, [x0] ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/fabs-fp128.ll b/llvm/test/CodeGen/AArch64/fabs-fp128.ll index 17b75f89b32da..903aa8adf7085 100644 --- a/llvm/test/CodeGen/AArch64/fabs-fp128.ll +++ b/llvm/test/CodeGen/AArch64/fabs-fp128.ll @@ -144,7 +144,7 @@ define <4 x fp128> @fabs_v4f128(<4 x fp128> %a) { ; CHECK-GI-LABEL: fabs_v4f128: ; CHECK-GI: // %bb.0: // %entry ; CHECK-GI-NEXT: mov x8, v0.d[1] -; CHECK-GI-NEXT: mov v0.d[0], v0.d[0] +; CHECK-GI-NEXT: mov v7.d[0], v0.d[0] ; CHECK-GI-NEXT: mov x9, v1.d[1] ; CHECK-GI-NEXT: mov x10, v2.d[1] ; CHECK-GI-NEXT: mov x11, v3.d[1] @@ -152,13 +152,14 @@ define <4 x fp128> @fabs_v4f128(<4 x fp128> %a) { ; CHECK-GI-NEXT: mov v2.d[0], v2.d[0] ; CHECK-GI-NEXT: mov v3.d[0], v3.d[0] ; CHECK-GI-NEXT: and x8, x8, #0x7fffffffffffffff -; CHECK-GI-NEXT: mov v0.d[1], x8 +; CHECK-GI-NEXT: mov v7.d[1], x8 ; CHECK-GI-NEXT: and x8, x9, #0x7fffffffffffffff ; CHECK-GI-NEXT: and x9, x10, #0x7fffffffffffffff ; CHECK-GI-NEXT: and x10, x11, #0x7fffffffffffffff ; CHECK-GI-NEXT: mov v1.d[1], x8 ; CHECK-GI-NEXT: mov v2.d[1], x9 ; CHECK-GI-NEXT: mov v3.d[1], x10 +; CHECK-GI-NEXT: mov v0.16b, v7.16b ; CHECK-GI-NEXT: ret entry: %c = call <4 x fp128> @llvm.fabs.v4f128(<4 x fp128> %a) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
