https://github.com/sdesmalen-arm created https://github.com/llvm/llvm-project/pull/207200
This just moves out some of the SVE lowering code from LowerVectorFP_TO_INT into a separate function, so that we can reuse that in LowerVectorFP_TO_INT_SAT. >From afad48d92e2a2bc28ef83f12875f497326934d4e Mon Sep 17 00:00:00 2001 From: Sander de Smalen <[email protected]> Date: Tue, 23 Jun 2026 13:30:27 +0000 Subject: [PATCH] [AArch64] NFC: Factor out code from FP_TO_INT (SVE). This just moves out some of the SVE lowering code from LowerVectorFP_TO_INT into a separate function, so that we can reuse that in LowerVectorFP_TO_INT_SAT. --- .../Target/AArch64/AArch64ISelLowering.cpp | 83 ++++++++++++------- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 5 +- 2 files changed, 58 insertions(+), 30 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index eb73ca84dbfee..4e61612aca96a 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -5078,28 +5078,8 @@ SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op, DAG.getNode(ISD::FP_EXTEND, DL, NewVT, Op.getOperand(0))); } - if (VT.isScalableVector()) { - if (VT.getVectorElementType() == MVT::i1) { - SDLoc DL(Op); - EVT CvtVT = getPromotedVTForPredicate(VT); - SDValue Cvt = DAG.getNode(Op.getOpcode(), DL, CvtVT, Op.getOperand(0)); - SDValue Zero = DAG.getConstant(0, DL, CvtVT); - return DAG.getSetCC(DL, VT, Cvt, Zero, ISD::SETNE); - } - - // Let common code split the operation. - if (InVT == MVT::nxv8f32) - return Op; - - unsigned Opcode = Op.getOpcode() == ISD::FP_TO_UINT - ? AArch64ISD::FCVTZU_MERGE_PASSTHRU - : AArch64ISD::FCVTZS_MERGE_PASSTHRU; - return LowerToPredicatedOp(Op, DAG, Opcode); - } - - if (useSVEForFixedLengthVectorVT(VT, !Subtarget->isNeonAvailable()) || - useSVEForFixedLengthVectorVT(InVT, !Subtarget->isNeonAvailable())) - return LowerFixedLengthFPToIntToSVE(Op, DAG); + if (SDValue Res = tryLowerFPToIntToSVE(Op, DAG)) + return Res; uint64_t VTSize = VT.getFixedSizeInBits(); uint64_t InVTSize = InVT.getFixedSizeInBits(); @@ -33951,18 +33931,63 @@ AArch64TargetLowering::LowerGET_ACTIVE_LANE_MASK(SDValue Op, DAG.getVectorIdxConstant(0, DL)); } -SDValue -AArch64TargetLowering::LowerFixedLengthFPToIntToSVE(SDValue Op, +SDValue AArch64TargetLowering::tryLowerFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const { + bool IsStrict = Op->isStrictFPOpcode(); + EVT InVT = Op.getOperand(IsStrict ? 1 : 0).getValueType(); EVT VT = Op.getValueType(); - assert(VT.isFixedLengthVector() && "Expected fixed length vector type!"); - bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT; - unsigned Opcode = IsSigned ? AArch64ISD::FCVTZS_MERGE_PASSTHRU - : AArch64ISD::FCVTZU_MERGE_PASSTHRU; + unsigned NewOpcode; + switch (Op.getOpcode()) { + case ISD::FP_TO_UINT: + case ISD::STRICT_FP_TO_UINT: + NewOpcode = AArch64ISD::FCVTZU_MERGE_PASSTHRU; + break; + case ISD::FP_TO_SINT: + case ISD::STRICT_FP_TO_SINT: + NewOpcode = AArch64ISD::FCVTZS_MERGE_PASSTHRU; + break; + default: + llvm_unreachable("Unexpected opcode"); + } SDLoc DL(Op); - SDValue Val = Op.getOperand(0); + if (VT.isScalableVector()) { + // Optimize the i1 case by using setcc. + if (VT.getVectorElementType() == MVT::i1) { + EVT CvtVT = getPromotedVTForPredicate(VT); + SDValue Cvt = DAG.getNode(Op.getOpcode(), DL, CvtVT, Op.getOperand(0)); + SDValue Zero = DAG.getConstant(0, DL, CvtVT); + return DAG.getSetCC(DL, VT, Cvt, Zero, ISD::SETNE); + } + + // Let common code split the operation. + if (InVT == MVT::nxv8f32) + return Op; + + SmallVector<SDValue, 4> Operands; + Operands.push_back(getPredicateForVector(DAG, DL, VT)); + Operands.push_back(IsStrict ? Op.getOperand(1) : Op.getOperand(0)); + Operands.push_back(DAG.getPOISON(VT)); + return DAG.getNode(NewOpcode, DL, VT, Operands, Op->getFlags()); + } + + bool UseSVE = !Subtarget->isNeonAvailable(); + if (useSVEForFixedLengthVectorVT(VT, UseSVE) || + useSVEForFixedLengthVectorVT(InVT, UseSVE)) + return LowerFixedLengthFPToIntToSVE(Op, DAG, NewOpcode); + + return SDValue(); +} + +SDValue AArch64TargetLowering::LowerFixedLengthFPToIntToSVE( + SDValue Op, SelectionDAG &DAG, unsigned Opcode) const { + EVT VT = Op.getValueType(); + assert(VT.isFixedLengthVector() && "Expected fixed length vector type!"); + + SDLoc DL(Op); + bool IsStrict = Op->isStrictFPOpcode(); + SDValue Val = Op.getOperand(IsStrict ? 1 : 0); EVT SrcVT = Val.getValueType(); EVT ContainerDstVT = getContainerForFixedLengthVector(DAG, VT); EVT ContainerSrcVT = getContainerForFixedLengthVector(DAG, SrcVT); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 1341a4b3e03b6..8d966ba1fbcab 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -805,6 +805,8 @@ class AArch64TargetLowering : public TargetLowering { SDValue LowerFCANONICALIZE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const; + SDValue tryLowerFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op, @@ -829,7 +831,8 @@ class AArch64TargetLowering : public TargetLowering { SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG, + unsigned Opcode) const; SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFixedLengthBuildVectorToSVE(SDValue Op, SelectionDAG &DAG) const; _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
