================
@@ -890,3 +890,88 @@ body: |
S_ENDPGM 0
...
+
+---
+name: fold_s_mov_b32_inline_imm_valu_inst_0
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fold_s_mov_b32_inline_imm_valu_inst_0
+ ; GCN: liveins: $vgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
+ ; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]],
1, 0, implicit $exec
+ ; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_U32_e64_]]
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_32 = S_MOV_B32 1
+ %2:vgpr_32 = V_ADD_U32_e64 %0, %1, 0, implicit $exec
+ SI_RETURN_TO_EPILOG %2
+
+...
+
+---
+name: fold_s_mov_b32_inline_imm_valu_inst_1
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fold_s_mov_b32_inline_imm_valu_inst_1
+ ; GCN: liveins: $vgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
+ ; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 1,
[[COPY]], 0, implicit $exec
+ ; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_U32_e64_]]
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_32 = S_MOV_B32 1
+ %2:vgpr_32 = V_ADD_U32_e64 %1, %0, 0, implicit $exec
+ SI_RETURN_TO_EPILOG %2
+
+...
+
+---
+name: fold_s_mov_b32_inline_imm_valu_inst_with_multi_uses
+body: |
+ bb.0:
+
+ ; GCN-LABEL: name: fold_s_mov_b32_inline_imm_valu_inst_with_multi_uses
+ ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
+ ; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 1, 1, 0,
implicit $exec
+ ; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_U32_e64_]]
+ %0:sreg_32 = S_MOV_B32 1
+ %1:vgpr_32 = V_ADD_U32_e64 %0, %0, 0, implicit $exec
+ SI_RETURN_TO_EPILOG %1
+
+...
+
+---
+name: fold_s_mov_b64_inline_imm_valu_inst_with_multi_uses
+body: |
+ bb.0:
+
+ ; GCN-LABEL: name: fold_s_mov_b64_inline_imm_valu_inst_with_multi_uses
+ ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1
+ ; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 1, 0, 0,
implicit $exec
+ ; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_U32_e64_]]
+ %0:sreg_64 = S_MOV_B64 1
+ %1:vgpr_32 = V_ADD_U32_e64 %0.sub0, %0.sub1, 0, implicit $exec
+ SI_RETURN_TO_EPILOG %1
+
+...
+
+---
+name: fold_s_mov_b64_imm_subregs_partial_inline_imm_one_inst
+body: |
+ bb.0:
+
+ ; GCN-LABEL: name: fold_s_mov_b64_imm_subregs_partial_inline_imm_one_inst
+ ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4096
+ ; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64
[[S_MOV_B]].sub0, 0, 0, implicit $exec
+ ; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_U32_e64_]]
+ %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4096
+ %1:vgpr_32 = V_ADD_U32_e64 %0.sub0, %0.sub1, 0, implicit $exec
+ SI_RETURN_TO_EPILOG %1
+
+...
----------------
frederik-h wrote:
Document the f16 issue by a test case? The test runs for gfx1250.
```suggestion
...
---
name: fold_inline_imm_f16_pseudo_scalar_trans_restriction
body: |
bb.0:
; GCN-LABEL: name: fold_inline_imm_f16_pseudo_scalar_trans_restriction
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GCN-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 0, -1,
0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_S_EXP_F16_e64_]]
%0:sreg_32 = S_MOV_B32 -1
%1:sgpr_32 = V_S_EXP_F16_e64 0, %0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %1
...
```
The expected result would look like this:
```
---
name: fold_inline_imm_f16_pseudo_scalar_trans_restriction
body: |
bb.0:
; GFX942-LABEL: name: fold_inline_imm_f16_pseudo_scalar_trans_restriction
; GFX942: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GFX942-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 0,
-1, 0, 0, implicit $mode, implicit $exec
; GFX942-NEXT: SI_RETURN_TO_EPILOG [[V_S_EXP_F16_e64_]]
;
; GFX1250-LABEL: name: fold_inline_imm_f16_pseudo_scalar_trans_restriction
; GFX1250: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GFX1250-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 0,
[[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
; GFX1250-NEXT: SI_RETURN_TO_EPILOG [[V_S_EXP_F16_e64_]]
%0:sreg_32 = S_MOV_B32 -1
%1:sgpr_32 = V_S_EXP_F16_e64 0, %0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %1
...
```
https://github.com/llvm/llvm-project/pull/208423
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