https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/208894
Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 5ccdd1500d3f77a54ffd14d428f810de62438dae Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 25 Jun 2026 09:54:16 +0200 Subject: [PATCH] AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (10) Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll | 2 +- .../CodeGen/AMDGPU/combine-vload-extract.ll | 2 +- .../AMDGPU/commute-compares-scalar-float.ll | 4 ++-- .../AMDGPU/commute-frame-index-operand.mir | 2 +- llvm/test/CodeGen/AMDGPU/commute-op-sel.mir | 2 +- llvm/test/CodeGen/AMDGPU/commute-shifts.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/commute-vop3.mir | 4 ++-- .../AMDGPU/compute-known-bits-nofpclass.ll | 2 +- ...computeKnownBits-scalar-to-vector-crash.ll | 2 +- .../CodeGen/AMDGPU/computeNumSignBits-mul.ll | 2 +- llvm/test/CodeGen/AMDGPU/concat_vectors.ll | 4 ++-- .../AMDGPU/consecutive-loads-in-branch.ll | 2 +- .../AMDGPU/constant-address-space-32bit.ll | 8 ++++---- .../AMDGPU/constant-fold-imm-immreg.mir | 2 +- .../AMDGPU/constant-fold-mi-operands.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/constrained-shift.ll | 4 ++-- .../CodeGen/AMDGPU/convergence-laneops.ll | 4 ++-- .../test/CodeGen/AMDGPU/convergence-tokens.ll | 6 +++--- .../CodeGen/AMDGPU/copy-hoist-no-spills.ll | 2 +- llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll | 4 ++-- .../CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir | 2 +- .../CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir | 2 +- ...hys-reg-implicit-operand-kills-subregs.mir | 2 +- .../CodeGen/AMDGPU/copy-to-reg-frameindex.ll | 2 +- .../CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/copy-to-reg.ll | 4 ++-- .../AMDGPU/copy-vgpr-clobber-spill-vgpr.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir | 12 +++++------ llvm/test/CodeGen/AMDGPU/copy_to_scc.ll | 2 +- .../AMDGPU/copysign-simplify-demanded-bits.ll | 2 +- .../AMDGPU/copysign-to-disjoint-or-combine.ll | 2 +- .../AMDGPU/couldnt-join-subrange-3.mir | 2 +- .../AMDGPU/cross-block-use-is-not-abi-copy.ll | 2 +- llvm/test/CodeGen/AMDGPU/cse-convergent.ll | 2 +- .../CodeGen/AMDGPU/cse-phi-incoming-val.ll | 2 +- llvm/test/CodeGen/AMDGPU/csr-gfx10.ll | 4 ++-- .../AMDGPU/csr-sgpr-spill-live-ins.mir | 2 +- llvm/test/CodeGen/AMDGPU/ctls.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/ctlz.ll | 12 +++++------ llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/ctpop.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/ctpop16.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/ctpop64.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/cttz.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/cube.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 12 +++++------ llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll | 4 ++-- .../CodeGen/AMDGPU/dag-divergence-atomic.ll | 2 +- llvm/test/CodeGen/AMDGPU/dag-divergence.ll | 2 +- .../AMDGPU/dag-preserve-disjoint-flag.ll | 2 +- ...dagcomb-extract-vec-elt-different-sizes.ll | 2 +- llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll | 2 +- .../CodeGen/AMDGPU/dagcombine-fma-crash.ll | 4 ++-- .../CodeGen/AMDGPU/dagcombine-fma-fmad.ll | 4 ++-- .../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 20 +++++++++---------- .../dagcombine-reassociate-multi-memop.ll | 2 +- llvm/test/CodeGen/AMDGPU/dagcombine-select.ll | 4 ++-- .../CodeGen/AMDGPU/dagcombine-setcc-select.ll | 2 +- .../dagcombine-v1i8-extractvecelt-crash.ll | 2 +- .../test/CodeGen/AMDGPU/dbg-info-inline-at.ll | 2 +- .../AMDGPU/dbg-value-ends-sched-region.mir | 4 ++-- .../AMDGPU/dbg-value-starts-sched-region.mir | 2 +- .../AMDGPU/dead-frame-index-dbg-value.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/dead-lane.mir | 4 ++-- .../dead-machine-elim-after-dead-lane.ll | 2 +- llvm/test/CodeGen/AMDGPU/dead_bundle.mir | 2 +- llvm/test/CodeGen/AMDGPU/dead_copy.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/debug-frame.ll | 8 ++++---- ...debug-independence-dead-mi-elimination.mir | 4 ++-- .../debug-independence-exec-masking.mir | 2 +- .../AMDGPU/debug-value-scheduler-crash.mir | 4 ++-- .../AMDGPU/debug-value-scheduler-liveins.mir | 4 ++-- .../CodeGen/AMDGPU/debug-value-scheduler.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/debug.ll | 4 ++-- ...-work-group-size-overrides-waves-per-eu.ll | 2 +- .../CodeGen/AMDGPU/direct-indirect-call.ll | 2 +- .../CodeGen/AMDGPU/disable_form_clauses.ll | 2 +- .../CodeGen/AMDGPU/div-rem-by-constant-64.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/div_i128.ll | 8 ++++---- .../AMDGPU/diverge-extra-formal-args.ll | 6 +++--- .../AMDGPU/diverge-interp-mov-lower.ll | 12 +++++------ .../CodeGen/AMDGPU/diverge-switch-default.ll | 2 +- llvm/test/CodeGen/AMDGPU/divergence-at-use.ll | 2 +- .../CodeGen/AMDGPU/divergence-driven-abs.ll | 8 ++++---- .../AMDGPU/divergence-driven-buildvector.ll | 10 +++++----- .../divergence-driven-negsubinlineconst.ll | 8 ++++---- .../CodeGen/AMDGPU/divergence-driven-xnor.ll | 8 ++++---- .../divergent-branch-uniform-condition.ll | 2 +- llvm/test/CodeGen/AMDGPU/divrem24-assume.ll | 2 +- llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir | 2 +- .../CodeGen/AMDGPU/dpp_combine-true16.mir | 6 +++--- .../test/CodeGen/AMDGPU/dpp_combine_gfx11.mir | 6 +++--- .../CodeGen/AMDGPU/dpp_combine_gfx1250.mir | 2 +- 97 files changed, 210 insertions(+), 210 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll b/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll index 8a01964382623..5cd1cdd20781b 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-ftrunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}combine_ftrunc_frint_f64: ; GCN: v_rndne_f64_e32 [[RND:v\[[0-9:]+\]]], diff --git a/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll b/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll index 211174af632ee..a2bf889fe3297 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.0a < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @vectorLoadCombine(ptr %in, ptr %out) { ; GCN-LABEL: vectorLoadCombine: diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll b/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll index 369e3e796b273..6d8e78acdfc00 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=SDAG %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -mtriple=amdgpu11.50 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=SDAG %s +; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.50 -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GISEL %s define amdgpu_vs void @fcmp_f32_olt_to_ogt(ptr addrspace(1) inreg %out, float inreg %a) { ; SDAG-LABEL: fcmp_f32_olt_to_ogt: diff --git a/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir b/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir index a891d8f18e861..a8c541e9450f6 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir +++ b/llvm/test/CodeGen/AMDGPU/commute-frame-index-operand.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=machine-cse -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s # Check that invalid MIR is not produced with a frame index in a # commutable operand. diff --git a/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir b/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir index 9274c995dde92..322784815cf93 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir +++ b/llvm/test/CodeGen/AMDGPU/commute-op-sel.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=machine-cse -verify-machineinstrs %s -o - 2>&1 | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu10.30 -run-pass=machine-cse -verify-machineinstrs %s -o - 2>&1 | FileCheck --check-prefix=GCN %s --- name: test_machine_cse_op_sel_v_add_nc_u16 diff --git a/llvm/test/CodeGen/AMDGPU/commute-shifts.ll b/llvm/test/CodeGen/AMDGPU/commute-shifts.ll index d1fe78de375d1..969d77e63a11d 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-shifts.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-shifts.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.01 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=VI %s define amdgpu_ps float @main(float %arg0, float %arg1) #0 { ; SI-LABEL: main: diff --git a/llvm/test/CodeGen/AMDGPU/commute-vop3.mir b/llvm/test/CodeGen/AMDGPU/commute-vop3.mir index 9a8805effb5bd..7f93661f5482d 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-vop3.mir +++ b/llvm/test/CodeGen/AMDGPU/commute-vop3.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -run-pass=machine-cse -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -run-pass=machine-cse -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s +# RUN: llc -run-pass=machine-cse -mtriple=amdgpu9.00 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -run-pass=machine-cse -mtriple=amdgpu10.10 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s --- diff --git a/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll b/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll index 244c3f7c2a96a..75276dc1df889 100644 --- a/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll +++ b/llvm/test/CodeGen/AMDGPU/compute-known-bits-nofpclass.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s define i32 @known_positive(float nofpclass(nan ninf nzero nsub nnorm) %signbit.zero) #0 { ; CHECK-LABEL: known_positive: diff --git a/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll b/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll index b93ece7ca04f3..3a857395d69c8 100644 --- a/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx802 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck %s ; CHECK: s_waitcnt define <2 x i16> @main(<2 x float>) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll index 11795cca18daa..7691944970f50 100644 --- a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - -amdgpu-codegenprepare-mul24=0 < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -o - -amdgpu-codegenprepare-mul24=0 < %s | FileCheck -check-prefix=GFX9 %s define i16 @num_sign_bits_mul_i48_0(i8 %X, i8 %Y, i8 %Z, i8 %W) { ; GFX9-LABEL: num_sign_bits_mul_i48_0: diff --git a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll index 09f81011e03be..034139e2eef1c 100644 --- a/llvm/test/CodeGen/AMDGPU/concat_vectors.ll +++ b/llvm/test/CodeGen/AMDGPU/concat_vectors.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GCN,VI %s ; GCN-LABEL: {{^}}test_concat_v1i32: ; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF diff --git a/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll b/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll index f9f481f56fa7c..ceef5614bc94e 100644 --- a/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll +++ b/llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX12 %s define amdgpu_kernel void @straightline_kernel(ptr addrspace(1) noalias %in, ptr addrspace(1) noalias %out, i32 %base, i1 %cond) { ; GFX12-LABEL: straightline_kernel: diff --git a/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll b/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll index 11edef2929d7d..22fbbe3fe33b8 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll +++ b/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX67,GFX6 %s -; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GFX67,GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX89,GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX67,GFX6 %s +; RUN: llc -mtriple=amdgpu7.04 < %s | FileCheck -check-prefixes=GFX67,GFX7 %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX89,GFX8 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s define amdgpu_vs float @load_i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 { ; GFX67-LABEL: load_i32: diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index e843de15b90ec..5a2b055a110f8 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.00--amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination -o - %s | FileCheck -enable-var-scope -check-prefix=GCN %s ... # GCN-LABEL: name: s_fold_and_imm_regimm_32{{$}} diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll b/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll index 0691ae53d3bc5..d8e5935dc1323 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=verde < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.01--amdpal < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.02--amdpal -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}fold_mi_v_and_0: ; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}} diff --git a/llvm/test/CodeGen/AMDGPU/constrained-shift.ll b/llvm/test/CodeGen/AMDGPU/constrained-shift.ll index d7a21ce245d75..d2fee5930dd9c 100644 --- a/llvm/test/CodeGen/AMDGPU/constrained-shift.ll +++ b/llvm/test/CodeGen/AMDGPU/constrained-shift.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel < %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00 -global-isel < %s | FileCheck -check-prefix=GISEL %s define i16 @csh_16(i16 %a, i16 %b) { ; CHECK-LABEL: csh_16: diff --git a/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll b/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll index 57ab371d5b6fc..64a6edcc72c93 100644 --- a/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll +++ b/llvm/test/CodeGen/AMDGPU/convergence-laneops.ll @@ -1,5 +1,5 @@ -; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s -; RUN: not --crash llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s +; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgpu11.00-- -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s +; RUN: not --crash llc -mtriple=amdgpu11.00--amdhsa -verify-machineinstrs < %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s ; FIXME: Merge these tests with existing lane op tests (llvm.amdgcn.readlane.ll, llvm.amdgcn.writelane.ll ...) once the crash is fixed. diff --git a/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll b/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll index 61d102d2222bd..78909952aeb70 100644 --- a/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll +++ b/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll @@ -1,6 +1,6 @@ -; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx900 -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s -; RUN: llc -stop-after=dead-mi-elimination -mtriple=amdgcn-- -mcpu=gfx900 -o - %s | FileCheck --check-prefixes=CHECK,DEADMI %s -; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgcn-- -mcpu=gfx900 -o - %s | FileCheck %s --check-prefixes=CHECK,GISEL +; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgpu9.00-- -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s +; RUN: llc -stop-after=dead-mi-elimination -mtriple=amdgpu9.00-- -o - %s | FileCheck --check-prefixes=CHECK,DEADMI %s +; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgpu9.00-- -o - %s | FileCheck %s --check-prefixes=CHECK,GISEL ; CHECK-LABEL: name: basic_call ; CHECK: [[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL_ENTRY diff --git a/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll b/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll index 5f0c5106a675b..3fecc516f2b13 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll @@ -1,5 +1,5 @@ ; NOTE: There must be no spill reload inside the loop starting with LBB0_1: -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck %s define amdgpu_kernel void @foo(ptr %.sroa.1.0.copyload, ptr %0, ptr %1, ptr %2, ptr %3, ptr %4, ptr %5, ptr %6, ptr %7, ptr %8, ptr %9, ptr %10, ptr %11, ptr %12, ptr %13, ptr %14, ptr %15, ptr %16, ptr %17, ptr %18, ptr %19, ptr %20, ptr %21, ptr %22, ptr %23, ptr %24, ptr %25, ptr %26, ptr %27, ptr %28, ptr %29, ptr %30, ptr %31, ptr %32, ptr %33, double %34, double %35, double %36, float %37, float %38, float %39, float %40, ptr %41) { ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll index 7a576b1c58c55..8c2e0fa61d52e 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=VI %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir b/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir index 004830397c98b..41fce7e3a64bd 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir +++ b/llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s # Don't set a kill of the super register on the last instruction with # an overlapping copy. This would kill part of the values in the diff --git a/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir b/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir index 5286c6d34cf44..e4f1509f7770b 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir +++ b/llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s # Don't set a kill of the super register on the last instruction with # an overlapping copy. This would kill part of the values in the diff --git a/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir b/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir index 06a5cbbcb5238..ea1c308b7af02 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir +++ b/llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu10.31-amd-amdhsa -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s # The copy has an implicit def of a superregister which overlaps the # register it defines. We cannot preserve the kill on the tuple def diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll index a13f3513c660e..f7e9b8724b682 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx90a | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu9.0a | FileCheck %s define amdgpu_kernel void @copy_to_reg_frameindex(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) { ; CHECK-LABEL: copy_to_reg_frameindex: diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll index ac9a279491668..122c0f7068f4f 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=source < %s | FileCheck -check-prefix=RRLIST %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O3 -pre-RA-sched=fast < %s | FileCheck -check-prefix=FAST %s +; RUN: llc -mtriple=amdgpu9.0a -O3 -pre-RA-sched=source < %s | FileCheck -check-prefix=RRLIST %s +; RUN: llc -mtriple=amdgpu9.0a -O3 -pre-RA-sched=fast < %s | FileCheck -check-prefix=FAST %s define protected amdgpu_kernel void @sccClobber(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %e, ptr addrspace(1) %f, ptr addrspace(1) %pout.coerce) { diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll index f5223d5553c6a..6cc2af673f017 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=hawaii -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | FileCheck -check-prefix=GFX7 %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -mtriple=amdgpu7.01 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | FileCheck -check-prefix=GFX7 %s +; RUN: llc -mtriple=amdgpu8.02 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | FileCheck -check-prefix=GFX8 %s ; Test that CopyToReg instructions don't have non-register operands prior ; to being emitted. diff --git a/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir b/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir index 6132c4ea3e61d..0130b13c56d0e 100644 --- a/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -start-before=prolog-epilog %s -o - | FileCheck --check-prefix=GFX908 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -start-before=prolog-epilog %s -o - | FileCheck --check-prefix=GFX90A %s +# RUN: llc -mtriple=amdgpu9.08 -verify-machineinstrs -start-before=prolog-epilog %s -o - | FileCheck --check-prefix=GFX908 %s +# RUN: llc -mtriple=amdgpu9.0a -verify-machineinstrs -start-before=prolog-epilog %s -o - | FileCheck --check-prefix=GFX90A %s --- | diff --git a/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir b/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir index daeffdd7917dc..09cd36fb60e9a 100644 --- a/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir +++ b/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir @@ -1,10 +1,10 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX908 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX90A %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX942 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass postrapseudos %s -o - | FileCheck -check-prefix=GFX1250 %s +# RUN: llc -mtriple=amdgpu9.08 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX908 %s +# RUN: llc -mtriple=amdgpu9.0a -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX90A %s +# RUN: llc -mtriple=amdgpu9.42 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX942 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu11.00 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu12.50 -run-pass postrapseudos %s -o - | FileCheck -check-prefix=GFX1250 %s --- name: copy_v64_to_v64 diff --git a/llvm/test/CodeGen/AMDGPU/copy_to_scc.ll b/llvm/test/CodeGen/AMDGPU/copy_to_scc.ll index 1f4e20084da10..256145080a43f 100644 --- a/llvm/test/CodeGen/AMDGPU/copy_to_scc.ll +++ b/llvm/test/CodeGen/AMDGPU/copy_to_scc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @copy_to_scc(ptr addrspace(1) %out, ptr addrspace(1) %in, ptr addrspace(4) %addrSrc) { ; GCN-LABEL: copy_to_scc: diff --git a/llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll b/llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll index ce930036c8d59..60942be400d11 100644 --- a/llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll +++ b/llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s ; Test that we use SimplifyDemandedBits on copysign's sign ; operand. These are somewhat simplified extractions from fast pown diff --git a/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll b/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll index 3ca7dea0c4b08..ae83ba31f7587 100644 --- a/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s ; Negative test, don't know %x is positive define half @copysign_known_signmask_f16(half %x, i16 %sign) { diff --git a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir index 004abb4bb0ccd..fcbaf4d11d969 100644 --- a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir +++ b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck -check-prefix GCN %s +# RUN: llc -mtriple=amdgpu9.00--amdpal -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck -check-prefix GCN %s # --- name: _amdgpu_ps_main diff --git a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll index 1cf69b2530c35..4ffff7bd28ad4 100644 --- a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s ; SelectionDAG builder was using the IR value kind to decide how to ; split the types for copyToRegs/copyFromRegs in all contexts. This diff --git a/llvm/test/CodeGen/AMDGPU/cse-convergent.ll b/llvm/test/CodeGen/AMDGPU/cse-convergent.ll index 6b43742b5d892..1da122deacbd8 100644 --- a/llvm/test/CodeGen/AMDGPU/cse-convergent.ll +++ b/llvm/test/CodeGen/AMDGPU/cse-convergent.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=GCN +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck %s -check-prefix=GCN define i32 @test(i32 %val, i32 %cond) { ; GCN-LABEL: test: diff --git a/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll b/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll index 629042476040f..3fd1e90b653a5 100644 --- a/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll +++ b/llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu9.00--amdpal | FileCheck %s ; Check that the redundant immediate MOV instruction ; (by-product of handling phi nodes) is not found diff --git a/llvm/test/CodeGen/AMDGPU/csr-gfx10.ll b/llvm/test/CodeGen/AMDGPU/csr-gfx10.ll index deebe06490b36..1cb27a8513032 100644 --- a/llvm/test/CodeGen/AMDGPU/csr-gfx10.ll +++ b/llvm/test/CodeGen/AMDGPU/csr-gfx10.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -o - %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -o - %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -o - %s | FileCheck -check-prefix=GFX10 %s ; Make sure new higher SGPRs are callee saved ; GFX10-LABEL: {{^}}callee_new_sgprs: diff --git a/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir index c7aa1a1073a99..187a1c8b3d900 100644 --- a/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir +++ b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx906 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.06 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s # Make sure the modified CSR VGPRs are added as live-in to the entry # block. diff --git a/llvm/test/CodeGen/AMDGPU/ctls.ll b/llvm/test/CodeGen/AMDGPU/ctls.ll index e5c70fae90170..52d55d13064eb 100644 --- a/llvm/test/CodeGen/AMDGPU/ctls.ll +++ b/llvm/test/CodeGen/AMDGPU/ctls.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GFX6 %s +; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -check-prefix=GFX11 %s declare i32 @llvm.ctlz.i32(i32, i1) declare i64 @llvm.ctlz.i64(i64, i1) diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll index 594f036b391ed..37ab5cccea33b 100644 --- a/llvm/test/CodeGen/AMDGPU/ctlz.ll +++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck %s -enable-var-scope --check-prefix=SI -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s -enable-var-scope --check-prefix=VI +; RUN: llc < %s -mtriple=amdgpu6.00 | FileCheck %s -enable-var-scope --check-prefix=SI +; RUN: llc < %s -mtriple=amdgpu8.02 -mattr=-flat-for-global | FileCheck %s -enable-var-scope --check-prefix=VI ; RUN: llc < %s -mtriple=r600 -mcpu=cypress | FileCheck %s -enable-var-scope --check-prefix=EG -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10 -; RUN: llc < %s -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 +; RUN: llc < %s -mtriple=amdgpu10.10 | FileCheck %s -enable-var-scope --check-prefix=GFX10 +; RUN: llc < %s -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL +; RUN: llc < %s -mtriple=amdgpu11.00 -mattr=+real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 +; RUN: llc < %s -mtriple=amdgpu11.00 -mattr=-real-true16 | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll index af445d6a054f1..31a22c067a0fc 100644 --- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll +++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=VI %s ; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=EG %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-GISEL %s +; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9-GISEL %s declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone declare <2 x i7> @llvm.ctlz.v2i7(<2 x i7>, i1) nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/ctpop.ll b/llvm/test/CodeGen/AMDGPU/ctpop.ll index 06ab198746053..ec9bf36e76482 100644 --- a/llvm/test/CodeGen/AMDGPU/ctpop.ll +++ b/llvm/test/CodeGen/AMDGPU/ctpop.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=VI %s ; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s -; RUN: llc -mtriple=amdgcn -mcpu=tahiti -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefix=SI-GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefix=VI-GISEL %s +; RUN: llc -mtriple=amdgpu6.00 -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefix=SI-GISEL %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global -global-isel=1 < %s | FileCheck -enable-var-scope -check-prefix=VI-GISEL %s declare i32 @llvm.ctpop.i32(i32) nounwind readnone declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/ctpop16.ll b/llvm/test/CodeGen/AMDGPU/ctpop16.ll index ae534a1401db0..7cb4adfabed3c 100644 --- a/llvm/test/CodeGen/AMDGPU/ctpop16.ll +++ b/llvm/test/CodeGen/AMDGPU/ctpop16.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI %s ; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s -; RUN: llc -mtriple=amdgcn -mcpu=tahiti -global-isel=1 -global-isel-abort=2 < %s | FileCheck -enable-var-scope -check-prefixes=SI-GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -global-isel=1 -global-isel-abort=2 < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s +; RUN: llc -mtriple=amdgpu6.00 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -enable-var-scope -check-prefixes=SI-GISEL %s +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global -global-isel=1 -global-isel-abort=2 < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s declare i16 @llvm.ctpop.i16(i16) nounwind readnone declare <2 x i16> @llvm.ctpop.v2i16(<2 x i16>) nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/ctpop64.ll b/llvm/test/CodeGen/AMDGPU/ctpop64.ll index 60b95218105eb..b0f2d87466707 100644 --- a/llvm/test/CodeGen/AMDGPU/ctpop64.ll +++ b/llvm/test/CodeGen/AMDGPU/ctpop64.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefix=GFX12 %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/cttz.ll b/llvm/test/CodeGen/AMDGPU/cttz.ll index 6cab7f3edde31..1b964d35aadd9 100644 --- a/llvm/test/CodeGen/AMDGPU/cttz.ll +++ b/llvm/test/CodeGen/AMDGPU/cttz.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck %s -enable-var-scope --check-prefix=SI -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s -enable-var-scope --check-prefix=VI +; RUN: llc < %s -mtriple=amdgpu6.00 | FileCheck %s -enable-var-scope --check-prefix=SI +; RUN: llc < %s -mtriple=amdgpu8.02 -mattr=-flat-for-global | FileCheck %s -enable-var-scope --check-prefix=VI ; RUN: llc < %s -mtriple=r600 -mcpu=cypress | FileCheck %s -enable-var-scope --check-prefix=EG -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10 -; RUN: llc < %s -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL +; RUN: llc < %s -mtriple=amdgpu10.10 | FileCheck %s -enable-var-scope --check-prefix=GFX10 +; RUN: llc < %s -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10 | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL declare i7 @llvm.cttz.i7(i7, i1) nounwind readnone declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll index 1695100ae231a..090d488cd01e0 100644 --- a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll +++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=VI %s ; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=EG %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-GISEL %s +; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9-GISEL %s declare i7 @llvm.cttz.i7(i7, i1) nounwind readnone declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/cube.ll b/llvm/test/CodeGen/AMDGPU/cube.ll index 88416f3b8bcc7..8625ad36c2e89 100644 --- a/llvm/test/CodeGen/AMDGPU/cube.ll +++ b/llvm/test/CodeGen/AMDGPU/cube.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GCN %s declare float @llvm.amdgcn.cubeid(float, float, float) #0 declare float @llvm.amdgcn.cubesc(float, float, float) #0 diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll index 2f2434aa682da..179eeb2cdf3aa 100644 --- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll +++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck %s -check-prefixes=GCN,SI -; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s -check-prefixes=GCN,VI -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX10 -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx908 -start-before=amdgpu-isel < %s | FileCheck %s -check-prefixes=GFX9 -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE16 -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE16 +; RUN: llc -mtriple=amdgpu6.00-- < %s | FileCheck %s -check-prefixes=GCN,SI +; RUN: llc -mtriple=amdgpu8.02-- -mattr=-flat-for-global < %s | FileCheck %s -check-prefixes=GCN,VI +; RUN: llc -mtriple=amdgpu10.10-- < %s | FileCheck %s -check-prefixes=GFX10 +; RUN: llc -mtriple=amdgpu9.08-- -start-before=amdgpu-isel < %s | FileCheck %s -check-prefixes=GFX9 +; RUN: llc -mtriple=amdgpu11.00-- -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE16 +; RUN: llc -mtriple=amdgpu11.00-- -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE16 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll b/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll index 2f27c4e3180aa..9e17becd70e5d 100644 --- a/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll +++ b/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI-SDAG %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -global-isel < %s | FileCheck -check-prefix=SI-GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel < %s | FileCheck -check-prefix=GFX11-GISEL %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI-SDAG %s +; RUN: llc -mtriple=amdgpu6.00 -global-isel < %s | FileCheck -check-prefix=SI-GISEL %s +; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -check-prefix=GFX11-SDAG %s +; RUN: llc -mtriple=amdgpu11.00 -global-isel < %s | FileCheck -check-prefix=GFX11-GISEL %s declare float @llvm.fabs.f32(float) #1 declare float @llvm.floor.f32(float) #1 diff --git a/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll b/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll index 4111b0c076ac9..03747cf0cc617 100644 --- a/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll +++ b/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI-SDAG %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -global-isel < %s | FileCheck -check-prefix=SI-GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel < %s | FileCheck -check-prefix=GFX11-GISEL %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI-SDAG %s +; RUN: llc -mtriple=amdgpu6.00 -global-isel < %s | FileCheck -check-prefix=SI-GISEL %s +; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -check-prefix=GFX11-SDAG %s +; RUN: llc -mtriple=amdgpu11.00 -global-isel < %s | FileCheck -check-prefix=GFX11-GISEL %s declare float @llvm.fabs.f32(float) #1 declare float @llvm.floor.f32(float) #1 diff --git a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll index c903d5b8428c1..7fe521102be99 100644 --- a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll +++ b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck -check-prefix=GFX12 %s ; Wait 0 bewteen load_d16_hi16 and or(v0.l,v0.l) define amdgpu_kernel void @d16_load_and_valu(ptr %in1, ptr %in2) { diff --git a/llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll b/llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll index db6d3fc205387..94e9395dd90e9 100644 --- a/llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll +++ b/llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-atomic-optimizer-strategy=None -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.0a -amdgpu-atomic-optimizer-strategy=None -o - %s | FileCheck %s %S = type <{ float, double }> diff --git a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll index 7b321141448de..b6f1c17275538 100644 --- a/llvm/test/CodeGen/AMDGPU/dag-divergence.ll +++ b/llvm/test/CodeGen/AMDGPU/dag-divergence.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @private_load_maybe_divergent(ptr addrspace(4) %k, ptr %flat) { ; GCN-LABEL: private_load_maybe_divergent: diff --git a/llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll b/llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll index a29688c0bdaa8..835802f799661 100644 --- a/llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll +++ b/llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -stop-after=finalize-isel -simplify-mir -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdpal -stop-after=finalize-isel -simplify-mir -o - %s | FileCheck %s ; Make sure disjoint flag is preserved on or instructions through selection diff --git a/llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll b/llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll index 9f12977a3efde..e5d1e2d250958 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -enable-var-scope %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck -enable-var-scope %s ; ; This code is used to trigger the following dag node, with different return type and vector element type: i16 extract_vec_elt <N x i8> v, 0 diff --git a/llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll b/llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll index 0f45e99dd76c4..9a08b424903a3 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s define i32 @mullohi_u32(i32 %arg, i32 %arg1, ptr %arg2) { ; CHECK-LABEL: mullohi_u32: diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll index 1ec2fb1ac3f67..3888365116799 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -enable-new-pm -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu10.30 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu10.30 -enable-new-pm -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s define void @main(float %arg) { ; CHECK-LABEL: name: main diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll index 3a158beb8ba91..4b713f66f35b9 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11 %s +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s +; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11 %s define amdgpu_ps float @_amdgpu_ps_main() #0 { ; GFX10-LABEL: _amdgpu_ps_main: diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll index aac2538fd3f24..1a00485907a47 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s define float @fmul_select_f32_test1(float %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX7-LABEL: fmul_select_f32_test1: diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll index 2b443e2178bb0..4d1a66f1340b1 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa < %s | FileCheck %s ; Test that DAGCombiner::reassociationCanBreakAddressingModePattern does not ; crash when a MemSDNode user has multiple memory operands (e.g. diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll index f5f122f86e0a6..29efadfeea127 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX942 %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgpu9.42 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX942 %s define amdgpu_kernel void @select_and1(ptr addrspace(1) %p, i32 %x, i32 %y) { ; GCN-LABEL: select_and1: diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll index 60194b617c843..99ed9d350360f 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s define amdgpu_kernel void @eq_t(float %x) { ; GCN-LABEL: eq_t: diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll index eecc91239c728..0bfd2c1e77052 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08 < %s | FileCheck %s define void @wombat(i1 %cond, ptr addrspace(5) %addr) { ; CHECK-LABEL: wombat: diff --git a/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll b/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll index 20077fa5d96a7..268c52e1c8820 100644 --- a/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll +++ b/llvm/test/CodeGen/AMDGPU/dbg-info-inline-at.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck %s define amdgpu_kernel void @_Z3fooPiiii(ptr addrspace(1) nocapture noundef writeonly %c.coerce, i32 noundef %a, i32 noundef %b, i32 noundef %d) !dbg !9 { ; CHECK-LABEL: _Z3fooPiiii: diff --git a/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir b/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir index b38dc4d21c10c..de68534fdfedc 100644 --- a/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir +++ b/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -passes=machine-scheduler -o - %s | FileCheck %s # The DBG_VALUE in bb.5 ends a scheduling region, and its uses should # not be tracked like a normal instruction. diff --git a/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir index 0785fe31d63b4..d55ed740d1a17 100644 --- a/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir +++ b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s # Verify we maintain live-ins even if the first instruction in sched region is # DBG_. diff --git a/llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll b/llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll index 235c4414ba64e..26e866d0227aa 100644 --- a/llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll +++ b/llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s ; Check that debug values referencing eliminated frame indices don't crash. ; The AMDGPU backend can eliminate spill slots during frame finalization diff --git a/llvm/test/CodeGen/AMDGPU/dead-lane.mir b/llvm/test/CodeGen/AMDGPU/dead-lane.mir index 8def0c3a15cf1..85f5d3dd49f0c 100644 --- a/llvm/test/CodeGen/AMDGPU/dead-lane.mir +++ b/llvm/test/CodeGen/AMDGPU/dead-lane.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -early-live-intervals -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu8.02 %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu8.02 %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -early-live-intervals -o - | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: dead_lane # GCN: bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll b/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll index f68b035334fd5..030dd754241fc 100644 --- a/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll +++ b/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 %s -o - | FileCheck %s ; After dead code elimination, that buffer load should be eliminated finally ; after dead lane detection. diff --git a/llvm/test/CodeGen/AMDGPU/dead_bundle.mir b/llvm/test/CodeGen/AMDGPU/dead_bundle.mir index d68a8dc9d1560..77d4a437d167d 100644 --- a/llvm/test/CodeGen/AMDGPU/dead_bundle.mir +++ b/llvm/test/CodeGen/AMDGPU/dead_bundle.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -verify-machineinstrs=1 -start-before=greedy,0 -stop-after=virtregrewriter,0 -stress-regalloc=5 %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu11.00--amdpal -verify-machineinstrs=1 -start-before=greedy,0 -stop-after=virtregrewriter,0 -stress-regalloc=5 %s -o - | FileCheck %s # This test checks that dead bundles are handled correctly. --- diff --git a/llvm/test/CodeGen/AMDGPU/dead_copy.mir b/llvm/test/CodeGen/AMDGPU/dead_copy.mir index 5bc42e9c47195..801c5d388b77d 100644 --- a/llvm/test/CodeGen/AMDGPU/dead_copy.mir +++ b/llvm/test/CodeGen/AMDGPU/dead_copy.mir @@ -1,5 +1,5 @@ -# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji -run-pass=machine-cp -verify-machineinstrs | FileCheck -check-prefix=GCN %s -# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji -passes=machine-cp | FileCheck -check-prefix=GCN %s +# RUN: llc -o - %s -mtriple=amdgpu8.03 -run-pass=machine-cp -verify-machineinstrs | FileCheck -check-prefix=GCN %s +# RUN: llc -o - %s -mtriple=amdgpu8.03 -passes=machine-cp | FileCheck -check-prefix=GCN %s # GCN-LABEL: dead_copy # GCN: bb.0 diff --git a/llvm/test/CodeGen/AMDGPU/debug-frame.ll b/llvm/test/CodeGen/AMDGPU/debug-frame.ll index ee48b43b06ad3..6190bfddaee1e 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-frame.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-frame.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck --check-prefixes=CHECK,GFX900 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-spill-vgpr-to-agpr=0 -o - %s | FileCheck --check-prefixes=CHECK,GFX90A-V2A-DIS %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-spill-vgpr-to-agpr=1 -o - %s | FileCheck --check-prefixes=CHECK,GFX90A-V2A-EN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - %s | FileCheck --check-prefixes=CHECK,WAVE32 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck --check-prefixes=CHECK,GFX900 %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -amdgpu-spill-vgpr-to-agpr=0 -o - %s | FileCheck --check-prefixes=CHECK,GFX90A-V2A-DIS %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -amdgpu-spill-vgpr-to-agpr=1 -o - %s | FileCheck --check-prefixes=CHECK,GFX90A-V2A-EN %s +; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -o - %s | FileCheck --check-prefixes=CHECK,WAVE32 %s define protected amdgpu_kernel void @kern1() #0 { ; CHECK-LABEL: kern1: diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir index a35eb170ea937..f30437a299277 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=dead-mi-elimination -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=dead-mi-elimination -o - %s -debugify-and-strip-all-safe | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=dead-mi-elimination -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=dead-mi-elimination -o - %s -debugify-and-strip-all-safe | FileCheck %s # Ensure that references in debug instructions to register results in dead # instructions do not prevent DCE. diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/debug-independence-exec-masking.mir index 0def0fc844d0d..d9437dfead691 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-independence-exec-masking.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-independence-exec-masking.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # REQUIRES: asserts -# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs -run-pass si-optimize-exec-masking %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.30 -verify-machineinstrs -run-pass si-optimize-exec-masking %s -o - | FileCheck %s # Ensure that debug instructions between a v_cmp and s_and_saveexec do not # crash si-optimize-exec-masking when walking live reg units backwards in diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir index 156979d6d06a5..1120d125a05e4 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -passes=machine-scheduler %s -o - | FileCheck %s --- | declare void @llvm.dbg.value(metadata, metadata, metadata) #0 diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir index 2a08c52e447ba..cbd3eed750010 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu9.08 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu9.08 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: ********** MI Scheduling ********** diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir index c02b38ebcfdce..df3d045a2e1e0 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir +++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu9.08 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu9.08 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: All regions recorded, starting actual scheduling. diff --git a/llvm/test/CodeGen/AMDGPU/debug.ll b/llvm/test/CodeGen/AMDGPU/debug.ll index 99200767ed736..9f95faa8b3812 100644 --- a/llvm/test/CodeGen/AMDGPU/debug.ll +++ b/llvm/test/CodeGen/AMDGPU/debug.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=amdgcn -mcpu=verde -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s -; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s +; RUN: llc < %s -mtriple=amdgpu6.01 -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s +; RUN: llc < %s -mtriple=amdgpu8.02 -mattr=dumpcode -filetype=obj | FileCheck --check-prefix=SI %s ; Test for a crash in the custom assembly dump code. diff --git a/llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll b/llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll index 67061bcb2a785..dc05258ac5904 100644 --- a/llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll +++ b/llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-unknown-unknown -mcpu=tahiti -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu6.00-unknown-unknown -passes=amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck %s ; Both of these kernels have the same value for ; amdgpu-flat-work-group-size, except one explicitly sets it. This is diff --git a/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll index e7674ee6423f8..085628c50e3e0 100644 --- a/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals -; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-attributor < %s | FileCheck %s define internal void @indirect() { ; CHECK-LABEL: define {{[^@]+}}@indirect diff --git a/llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll b/llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll index 4d969bf6d341f..0e59950c8fef7 100644 --- a/llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll +++ b/llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx902 -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.02 -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause ; GCN: S_LOAD_DWORDX4 diff --git a/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll b/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll index 95385b7cb14bc..c6d40b4cf4ac6 100644 --- a/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll +++ b/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -o - %s | FileCheck -check-prefixes=GFX942 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx9-4-generic --amdhsa-code-object-version=6 -o - %s | FileCheck -check-prefixes=GFX942 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -o - %s | FileCheck -check-prefixes=GFX1030 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -o - %s | FileCheck -check-prefixes=GFX942 %s +; RUN: llc -mtriple=amdgpu9.4-amd-amdhsa --amdhsa-code-object-version=6 -o - %s | FileCheck -check-prefixes=GFX942 %s +; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -o - %s | FileCheck -check-prefixes=GFX1030 %s ; Sample test to check how we deal with division/modulos by 64 bit constants. diff --git a/llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll b/llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll index ebd75e7e60552..eb14bd3b0fcdf 100644 --- a/llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll +++ b/llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix GFX950 %s -; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefix GFX90A %s +; RUN: llc -O0 -mtriple=amdgpu9.50 < %s | FileCheck --check-prefix GFX950 %s +; RUN: llc -O0 -mtriple=amdgpu9.0a < %s | FileCheck --check-prefix GFX90A %s ; Verify div/rem lowering at -O0 for operands that do or do not qualify for the ; float-reciprocal fast path. diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index 7fe8a61bbac8e..0b067ebbee0e3 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9 %s -; RUN: llc -O0 -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9-O0 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -O0 -global-isel=0 -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck -check-prefixes=GFX9-O0 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9-G %s -; RUN: llc -O0 -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9-G-O0 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck -check-prefixes=GFX9-G %s +; RUN: llc -O0 -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdhsa -o - %s | FileCheck -check-prefixes=GFX9-G-O0 %s define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-LABEL: v_sdiv_i128_vv: diff --git a/llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll b/llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll index 40ab75045c3d3..2b02567782ce5 100644 --- a/llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll +++ b/llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefix=GCN %s -; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx810 | FileCheck --check-prefix=GCN %s -; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc < %s -mtriple=amdgpu8.02--amdpal | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -mtriple=amdgpu8.10--amdpal | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -mtriple=amdgpu9.00--amdpal | FileCheck -check-prefixes=GCN,GFX9 %s ; A test case that originally failed in divergence calculation ; Implementation has to identify all formal args that can be a source of divergence diff --git a/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll b/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll index fed3cff82be9c..ea715f82f073c 100644 --- a/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll +++ b/llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefix=GCN %s -; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefix=GCN %s -; RUN: llc < %s -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx810 | FileCheck --check-prefix=GCN %s -; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdpal -mcpu=gfx810 | FileCheck --check-prefix=GCN %s -; RUN: llc < %s -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx900 | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdpal -mcpu=gfx900 | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc < %s -global-isel=0 -mtriple=amdgpu8.02--amdpal | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02--amdpal | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -global-isel=0 -mtriple=amdgpu8.10--amdpal | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.10--amdpal | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -global-isel=0 -mtriple=amdgpu9.00--amdpal | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00--amdpal | FileCheck -check-prefixes=GCN,GFX9 %s ; Testing for failures in divergence calculations when divergent intrinsic is lowered during instruction selection diff --git a/llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll b/llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll index 2895a52b6fcc8..f100478b00c0d 100644 --- a/llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll +++ b/llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -print-after=si-annotate-control-flow %s -filetype=null 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00 -print-after=si-annotate-control-flow %s -filetype=null 2>&1 | FileCheck %s ; CHECK-LABEL: @switch_unreachable_default diff --git a/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll b/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll index 955b5389c0dcd..32031fdddec08 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 - < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00 - < %s | FileCheck %s @local = addrspace(3) global i32 poison diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll index 1c82acf852d95..5ea90fabe764f 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgpu9.00 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgpu9.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s ; GCN-LABEL: name: s_abs_i32 ; GCN: S_ABS_I32 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll index d92d269615baa..015185fcea7d9 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu9.06 < %s | FileCheck -check-prefix=GFX906 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s define amdgpu_kernel void @uniform_vec_0_i16(ptr addrspace(1) %out, i16 %a) { ; GCN-LABEL: uniform_vec_0_i16: diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll index 0bcac198472e5..83ed82e9afc47 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgpu9.00 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgpu9.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s ; GCN-LABEL: name: uniform_add_SIC ; GCN: S_SUB_I32 killed %{{[0-9]+}}, 32 diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll index 49e836666084e..fbb9eae90c487 100644 --- a/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll +++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s +; RUN: llc -mtriple=amdgpu6.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.06 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s +; RUN: llc -mtriple=amdgpu6.00 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.06 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s ; GCN-LABEL: name: uniform_xnor_i64 ; GCN: S_XNOR_B64 diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll index 92fb345851479..68abe6a409e66 100644 --- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll +++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll @@ -4,7 +4,7 @@ ; checks are looking for the absence of specific metadata, which ; cannot be expressed reliably by the generated checks. -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=ISA +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s -check-prefix=ISA ; RUN: opt --amdgpu-annotate-uniform -S %s | FileCheck %s -check-prefix=UNIFORM ; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s | FileCheck %s -check-prefix=CONTROLFLOW diff --git a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll index c65a3bf1de30c..d60dc563ff020 100644 --- a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll +++ b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck %s +; RUN: opt -S -mtriple=amdgpu8.02-- -amdgpu-codegenprepare %s | FileCheck %s define amdgpu_kernel void @divrem24_assume(ptr addrspace(1) %arg, i32 %arg1) { ; CHECK-LABEL: @divrem24_assume( diff --git a/llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir b/llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir index 2beaf9a2bb2e4..8b35d0cfb82b0 100644 --- a/llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/do-not-fold-copy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=si-fold-operands -o - %s | FileCheck %s --- liveins: diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir index 792acda60620e..0d42d342fcfda 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir @@ -1,6 +1,6 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=gcn-dpp-combine -mattr=+real-true16 -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN -# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=gcn-dpp-combine -mattr=+real-true16 -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN -# XUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=gcn-dpp-combine -mattr=+real-true16 -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1150 +# RUN: llc -mtriple=amdgpu11.00 -run-pass=gcn-dpp-combine -mattr=+real-true16 -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu11.50 -run-pass=gcn-dpp-combine -mattr=+real-true16 -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN +# XUN: llc -mtriple=amdgpu12.00 -run-pass=gcn-dpp-combine -mattr=+real-true16 -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1150 # FIXME-TRUE16 add gfx1200 runline when we have those true16 instructions supported diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir index fd5a662815e21..b7c884c7995e7 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir @@ -1,6 +1,6 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX_NO_SRC1_SGPR -# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX_SRC1_SGPR -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX_SRC1_SGPR +# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX_NO_SRC1_SGPR +# RUN: llc -mtriple=amdgpu11.50 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX_SRC1_SGPR +# RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX_SRC1_SGPR --- diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir index 9972ec82f63cd..9c917df601dff 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=gcn-dpp-combine -o - %s | FileCheck %s -check-prefix=GFX1250 +# RUN: llc -mtriple=amdgpu12.50 -run-pass=gcn-dpp-combine -o - %s | FileCheck %s -check-prefix=GFX1250 --- name: v_bitop3_dpp _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
