llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-transforms Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 136.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/208895.diff 99 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/dpp64_combine.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/dpp64_combine.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/dpp_combine.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/dpp_combine.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds-alignment.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds_gws_align.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds_read2.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds_read2st64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/ds_write2.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ds_write2st64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dumpcode.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-indirect.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dvgpr_sym.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16_anon.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/early-if-convert.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/early-inline-alias.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/early-inline.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/early-lis-two-address-partial-def.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/early-term.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/eh_frame.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll (+79-79) - (modified) llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll (+14-14) - (modified) llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll (+18-18) - (modified) llvm/test/CodeGen/AMDGPU/elf-note-null-terminator.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/elf.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/elf.metadata.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir (+9-9) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir (+9-9) - (modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/else.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/emit-high-vgprs.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/empty-function.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/empty-text.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/expand-atomicrmw-syncscope.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling-no-outstanding.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx1250.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/export-cluster-postra.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extload-private.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extload.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/extra-lds-size.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extract-lowbits.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/extract-vector-elt-binop-build-vector.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fabs-known-signbit-combine-fast-fdiv-lowering.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fabs.bf16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fabs.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fabs.ll (+2-2) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll b/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll index 9df413b996764..f00def47d2ee9 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll +++ b/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A,DPP64-GFX9 -DCTL=row_newbcast -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64,DPP64-GFX9,GFX942 -DCTL=row_newbcast -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS,GFX10 -DCTL=row_share -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS,GFX11 -DCTL=row_share -; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX1250 -DCTL=row_share -; RUN: llc -mtriple=amdgcn -mcpu=gfx1251 < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64,DPP64-GFX1251 -DCTL=row_share +; RUN: llc -mtriple=amdgpu9.0a < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A,DPP64-GFX9 -DCTL=row_newbcast +; RUN: llc -mtriple=amdgpu9.42 < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64,DPP64-GFX9,GFX942 -DCTL=row_newbcast +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS,GFX10 -DCTL=row_share +; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS,GFX11 -DCTL=row_share +; RUN: llc -mtriple=amdgpu12.50 < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX1250 -DCTL=row_share +; RUN: llc -mtriple=amdgpu12.51 < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64,DPP64-GFX1251 -DCTL=row_share ; GCN-LABEL: {{^}}dpp64_ceil: ; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]], diff --git a/llvm/test/CodeGen/AMDGPU/dpp64_combine.mir b/llvm/test/CodeGen/AMDGPU/dpp64_combine.mir index 8094dbaf418b8..6712d8a4f5f72 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp64_combine.mir +++ b/llvm/test/CodeGen/AMDGPU/dpp64_combine.mir @@ -1,6 +1,6 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN -# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN -# RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -run-pass=gcn-dpp-combine -o - %s | FileCheck %s --check-prefix=GCN +# RUN: llc -mtriple=amdgpu9.0a -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN +# RUN: llc -mtriple=amdgpu9.42 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN +# RUN: llc -mtriple=amdgpu12.51 -run-pass=gcn-dpp-combine -o - %s | FileCheck %s --check-prefix=GCN --- # GCN-LABEL: name: dpp64_old_impdef diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine.ll b/llvm/test/CodeGen/AMDGPU/dpp_combine.ll index a56604c6f198b..68d3bee1ac635 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine.ll +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine.ll @@ -1,13 +1,13 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GCN,GFX9GFX10 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GCN,GFX9GFX10 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,NO_SRC1_SGPR -; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,SRC1_SGPR -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,SRC1_SGPR -; RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,SRC1_SGPR +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s -check-prefixes=GCN,GFX9GFX10 +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck %s -check-prefixes=GCN,GFX9GFX10 +; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,NO_SRC1_SGPR +; RUN: llc -mtriple=amdgpu11.50 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 +; RUN: llc -mtriple=amdgpu11.50 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,SRC1_SGPR +; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 +; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,SRC1_SGPR +; RUN: llc -mtriple=amdgpu12.51 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16 +; RUN: llc -mtriple=amdgpu12.51 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16,SRC1_SGPR ; GCN-LABEL: {{^}}dpp_add: ; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]], diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine.mir index 179d0becf6693..140a509bcbc34 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine.mir +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN +# RUN: llc -mtriple=amdgpu9.00 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN +# RUN: llc -mtriple=amdgpu9.00 -passes=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN --- # old is undefined: only combine when masks are fully enabled and diff --git a/llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll b/llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll index 6945d3ad18728..5bbc51e63c221 100644 --- a/llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.04 < %s | FileCheck -check-prefix=GCN %s ; The memory operand was dropped from the buffer_load_dword_offset ; when replaced with the addr64 during operand legalization, resulting diff --git a/llvm/test/CodeGen/AMDGPU/ds-alignment.ll b/llvm/test/CodeGen/AMDGPU/ds-alignment.ll index 4ddf17c8aaa9c..16a998bb5e9bf 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-alignment.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -mattr=-unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,ALIGNED,ALIGNED-SDAG -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -mattr=-unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,ALIGNED,ALIGNED-GISEL -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED,UNALIGNED-SDAG -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED,UNALIGNED-GISEL +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 -mattr=-unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,ALIGNED,ALIGNED-SDAG +; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -mattr=-unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,ALIGNED,ALIGNED-GISEL +; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED,UNALIGNED-SDAG +; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED,UNALIGNED-GISEL ; FixMe: need to decide to move multiple instructions to vgpr that will be folded by isel pattern diff --git a/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll b/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll index 842b912efefaa..6dcdcb69ad1cf 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgpu8.02--amdhsa < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -mtriple=amdgpu9.00--amdhsa < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: ds_read32_combine_stride_400: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[8:9], 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll b/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll index 0497542e11a8b..a13b303b15d7b 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN %s +; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN %s ; There is no dependence between the store and the two loads. So we can combine diff --git a/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll b/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll index c019a66fa12fe..e888008d80871 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s +; RUN: llc -mtriple=amdgpu7.04 -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s declare i32 @llvm.amdgcn.workitem.id.x() #0 declare void @llvm.amdgcn.s.barrier() #1 diff --git a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll index 03495a5a0fbff..b3a3a534e2c09 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: opt -passes=debugify < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s +; RUN: opt -passes=debugify < %s | llc -mtriple=amdgpu9.00-amd-amdhsa | FileCheck %s @lds = addrspace(3) global [512 x float] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll index af9dbc5052dc2..0e1d13ef2a6b0 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire < %s | FileCheck -enable-var-scope --check-prefix=CI %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu7.04--amdpal < %s | FileCheck -enable-var-scope --check-prefix=CI %s +; RUN: llc -mtriple=amdgpu9.00--amdpal < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu10.10--amdpal < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00--amdpal -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00--amdpal -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s declare i32 @llvm.amdgcn.workitem.id.x() #0 diff --git a/llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll b/llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll index 46ba8cb654c42..a4aface8fc28c 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-vectorization-alignment.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --enable-var-scope --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck --enable-var-scope --check-prefix=GCN %s ; Check that vectorizer does not create slow misaligned loads diff --git a/llvm/test/CodeGen/AMDGPU/ds_gws_align.ll b/llvm/test/CodeGen/AMDGPU/ds_gws_align.ll index d860602492f0c..855480ffee831 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_gws_align.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_gws_align.ll @@ -1,8 +1,8 @@ -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -early-live-intervals -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s +; RUN: llc -mtriple=amdgpu9.08-mesa-mesa3d -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s +; RUN: llc -mtriple=amdgpu9.0a-mesa-mesa3d -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s +; RUN: llc -global-isel -mtriple=amdgpu9.08-mesa-mesa3d -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s +; RUN: llc -global-isel -mtriple=amdgpu9.0a-mesa-mesa3d -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s +; RUN: llc -mtriple=amdgpu9.08-mesa-mesa3d -early-live-intervals -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s ; GCN-LABEL: {{^}}gws_init_odd_reg: ; GFX908-DAG: ds_gws_init v1 gds diff --git a/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll index 5cd798d4f6db1..b8abb2110bb07 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.0a < %s | FileCheck %s ; Try to stress ds.bpermute and ds.permute instructions with AGPR/AV ; inputs. It's not permissible to mix AGPRs and VGPR data operands. diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll index 8c28e037cdb3c..b98f7219e8beb 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1250 -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-UNALIGNED %s +; RUN: llc -mtriple=amdgpu12.50--amdpal -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-UNALIGNED %s ; FIXME: We don't get cases where the address was an SGPR because we ; get a copy to the address register for each one. diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll index 4e54ad43ff2a9..16b451699a9b1 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -enable-var-scope --check-prefix=CI %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=+load-store-opt,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s +; RUN: llc -mtriple=amdgpu7.04--amdpal -mattr=+load-store-opt < %s | FileCheck -enable-var-scope --check-prefix=CI %s +; RUN: llc -mtriple=amdgpu9.00--amdpal -mattr=+load-store-opt,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s +; RUN: llc -mtriple=amdgpu9.00--amdpal -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s ; FIXME: We don't get cases where the address was an SGPR because we ; get a copy to the address register for each one. diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll b/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll index 739aad35dcef8..572cd982fae42 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -strict-whitespace -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -strict-whitespace -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu7.04 < %s | FileCheck -strict-whitespace -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -strict-whitespace -check-prefix=SI %s @lds = addrspace(3) global [512 x float] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll b/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll index 37f56aaa0aec6..94a737877adef 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt,-enable-ds128 < %s | FileCheck --check-prefix=CI %s +; RUN: llc -mtriple=amdgpu7.04 -mattr=+load-store-opt,-enable-ds128 < %s | FileCheck --check-prefix=CI %s @lds = addrspace(3) global [512 x float] poison, align 4 @lds.v2 = addrspace(3) global [512 x <2 x float>] poison, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll b/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll index 1c425d1826908..b56480bb6a1cb 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgpu7.04 -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -mtriple=amdgpu9.00 -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s @lds = addrspace(3) global [512 x float] poison, align 4 @lds.f64 = addrspace(3) global [512 x double] poison, align 8 diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2.ll b/llvm/test/CodeGen/AMDGPU/ds_write2.ll index f05d248a52b15..6039f815c98b9 100644 --- a/llvm/test/CodeGen/AMDGPU/ds_write2.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_write2.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -enable-v... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/208895 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
