llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 134.04 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/208896.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/fadd.f16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fadd.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fadd64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.ll (+18-18) - (modified) llvm/test/CodeGen/AMDGPU/fceil.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fceil64.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fcmp.f16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fcmp64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fconst64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fcopysign.gfx11plus.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fdiv.f16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fdiv.f64.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fdiv.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/fdot2.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fence-barrier.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ffloor.f64.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/ffloor.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/finalizebundle.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-block-end-iterator-debugloc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-av-classes.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-readfirstlane-av-register-regression.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-sgpr32-to-vgpr16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wmma-scale-lo256.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/flat-address-space.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll (+15-15) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll (+10-10) - (modified) llvm/test/CodeGen/AMDGPU/flat-scratch.ll (+14-14) - (modified) llvm/test/CodeGen/AMDGPU/flat_atomics.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fma-combine.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fma-mix.gfx11plus.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fma.f16.ll (+12-12) - (modified) llvm/test/CodeGen/AMDGPU/fma.f64.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/fma.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll (+14-14) - (modified) llvm/test/CodeGen/AMDGPU/fmamk_fmaak-t16.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll (+5-5) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/fadd.f16.ll index c544c9e0cee4e..6f921981ac212 100644 --- a/llvm/test/CodeGen/AMDGPU/fadd.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fadd.f16.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn -mcpu=tahiti -enable-misched=false < %s | FileCheck -check-prefixes=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=VI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-SDAG %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -global-isel-abort=2 -mattr=+real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16-SDAG %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -global-isel-abort=2 -mattr=-real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16-GISEL %s +; RUN: llc -mtriple=amdgpu6.00 -enable-misched=false < %s | FileCheck -check-prefixes=SI %s +; RUN: llc -mtriple=amdgpu8.03 -mattr=-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=VI %s +; RUN: llc -mtriple=amdgpu11.00 -global-isel=0 -mattr=+real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-SDAG %s +; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -global-isel-abort=2 -mattr=+real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-GISEL %s +; RUN: llc -mtriple=amdgpu11.00 -global-isel=0 -mattr=-real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16-SDAG %s +; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -global-isel-abort=2 -mattr=-real-true16,-flat-for-global -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16-GISEL %s define amdgpu_kernel void @fadd_f16( ; SI-LABEL: fadd_f16: diff --git a/llvm/test/CodeGen/AMDGPU/fadd.ll b/llvm/test/CodeGen/AMDGPU/fadd.ll index 97cd979fb353f..834d971e69baa 100644 --- a/llvm/test/CodeGen/AMDGPU/fadd.ll +++ b/llvm/test/CodeGen/AMDGPU/fadd.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC -; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC +; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; FUNC-LABEL: {{^}}fadd_f32: diff --git a/llvm/test/CodeGen/AMDGPU/fadd64.ll b/llvm/test/CodeGen/AMDGPU/fadd64.ll index 27c4909a705a5..267751f68cc78 100644 --- a/llvm/test/CodeGen/AMDGPU/fadd64.ll +++ b/llvm/test/CodeGen/AMDGPU/fadd64.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck %s ; CHECK-LABEL: {{^}}v_fadd_f64: ; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} diff --git a/llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir b/llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir index 01cd5f74dcb48..555311c1d628c 100644 --- a/llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir +++ b/llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=regallocfast -o - %s | FileCheck %s -# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=regallocfast -o - %s | FileCheck %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu9.00-amd-amdhsa -run-pass=regallocfast -o - %s | FileCheck %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu9.00-amd-amdhsa -passes=regallocfast -o - %s | FileCheck %s # Make sure incorrect kills aren't emitted on vcc diff --git a/llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir b/llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir index 8c969eb0ef9b6..d430b7d5d74c8 100644 --- a/llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir +++ b/llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx902 -verify-machineinstrs -run-pass=regallocfast %s -o - | FileCheck --check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx902 -verify-machineinstrs -passes=regallocfast %s -o - | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.02 -verify-machineinstrs -run-pass=regallocfast %s -o - | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.02 -verify-machineinstrs -passes=regallocfast %s -o - | FileCheck --check-prefix=GCN %s --- name: fast_regalloc_bundle_handling diff --git a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll index 5259d20664d3f..b42690eb3bf2b 100644 --- a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll +++ b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=-unaligned-access-mode < %s | FileCheck --check-prefix=GFX7-ALIGNED %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX7-UNALIGNED %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX9 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX11 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX12 %s +; RUN: llc -mtriple=amdgpu7.01-amd-amdhsa -mattr=-unaligned-access-mode < %s | FileCheck --check-prefix=GFX7-ALIGNED %s +; RUN: llc -mtriple=amdgpu7.01-amd-amdhsa -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX7-UNALIGNED %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -mattr=+unaligned-access-mode < %s | FileCheck --check-prefix=GFX12 %s ; Should not merge this to a dword load define i32 @global_load_2xi16_align2(ptr addrspace(1) %p) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll index 6f8da57e223e5..345cef60501b8 100644 --- a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll +++ b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=-unaligned-scratch-access < %s | FileCheck --check-prefix=GFX7-ALIGNED %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX7-UNALIGNED %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX9 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX9-FLASTSCR %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX10-FLASTSCR %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX11 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX11-FLASTSCR %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX12 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX12-FLASTSCR %s +; RUN: llc -mtriple=amdgpu7.01-amd-amdhsa -mattr=-unaligned-scratch-access < %s | FileCheck --check-prefix=GFX7-ALIGNED %s +; RUN: llc -mtriple=amdgpu7.01-amd-amdhsa -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX7-UNALIGNED %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX9-FLASTSCR %s +; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX10-FLASTSCR %s +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX11-FLASTSCR %s +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -mattr=+unaligned-scratch-access < %s | FileCheck --check-prefix=GFX12 %s +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -mattr=+unaligned-scratch-access -mattr=+enable-flat-scratch < %s | FileCheck --check-prefix=GFX12-FLASTSCR %s ; Should not merge this to a dword load define i32 @private_load_2xi16_align2(ptr addrspace(5) %p) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir b/llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir index 6a2a2b0c3939f..0aaa6a7197396 100644 --- a/llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir +++ b/llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regallocfast -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes=regallocfast -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass=regallocfast -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -passes=regallocfast -o - %s | FileCheck %s # This would hit "Illegal subregister index for physical register" verifier error since # tied operands would skip dropping the subregister index. diff --git a/llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir b/llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir index 918242e9f9967..dd4ffae7b0158 100644 --- a/llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir +++ b/llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=regallocfast -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=regallocfast -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu9.00-amd-amdhsa -run-pass=regallocfast -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu9.00-amd-amdhsa -passes=regallocfast -o - %s | FileCheck -check-prefix=GCN %s --- name: self_loop_single_def_use diff --git a/llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir b/llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir index c57919d634dd6..22908c4834b63 100644 --- a/llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir +++ b/llvm/test/CodeGen/AMDGPU/fastregalloc-sgpr-only.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=regallocfast,0 --stop-after=regallocfast,0 -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -O0 -mtriple=amdgpu9.00-amd-amdhsa -start-before=regallocfast,0 --stop-after=regallocfast,0 -o - %s | FileCheck -check-prefix=GCN %s --- name: copy_vgpr_allocation diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll index 0896a540d09d0..4f83a0a105f10 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.bf16.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GCN,FAKE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GCN,REAL16 %s +; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GCN,FAKE16 %s +; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GCN,REAL16 %s define float @test_canonicalize_amdgcn_tanh_f32(float %a) { ; GCN-LABEL: test_canonicalize_amdgcn_tanh_f32: diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll index 1bbadaac9464c..125c9f09be8b1 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx801 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-FLUSH,GCN-FLUSH %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx801 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-DENORM,GCN-DENORM %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-DENORM,GCN-DENORM %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-FLUSH,GCN-FLUSH %s +; RUN: llc -mtriple=amdgpu8.01 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-FLUSH,GCN-FLUSH %s +; RUN: llc -mtriple=amdgpu8.01 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-DENORM,GCN-DENORM %s +; RUN: llc -mtriple=amdgpu9.00 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-DENORM,GCN-DENORM %s +; RUN: llc -mtriple=amdgpu9.00 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-FLUSH,GCN-FLUSH %s ; GCN-LABEL: {{^}}test_no_fold_canonicalize_loaded_value_f32: ; VI: v_mul_f32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}} diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll index 68d9cdf4730f3..30290e8565eab 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,FAKE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,REAL16 %s +; RUN: llc -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,FAKE16 %s +; RUN: llc -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,REAL16 %s declare bfloat @llvm.fabs.bf16(bfloat) #0 declare bfloat @llvm.canonicalize.bf16(bfloat) #0 diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll index 43a872787621a..4a828236f5a3c 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=VI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=kaveri < %s | FileCheck -enable-var-scope -check-prefixes=CI %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -enable-var-scope -check-prefixes=VI %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgpu7.00 < %s | FileCheck -enable-var-scope -check-prefixes=CI %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s declare half @llvm.fabs.f16(half) #0 declare half @llvm.canonicalize.f16(half) #0 diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll index 71370ef04365c..845fd53895074 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll @@ -1,22 +1,22 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GFX678,GFX678-SDAG,GFX6-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GFX678,GFX678-GISEL,GFX6-GISEL %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GFX678,GFX678-SDAG,GFX8-SDAG %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GFX678,GFX678-GISEL,GFX8-GISEL %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s -; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-TRUE16 %s -; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-TRUE16 %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-FAKE16 %s -; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-FAKE16 %s -; RUN: llc -amdgpu-scalarize-gl... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/208896 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
