llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-transforms Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 102.98 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209118.diff 97 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/global-constant.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/global-directive.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/global-extload-i16.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/global-saddr-load.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/global-saddr-store.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/group-image-instructions.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/gv-offset-folding.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/gws-hazards.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/gws_agpr.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/half-alloca-promotion.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/half.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/hard-clause-limit-attr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hard-clause-limit.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/hard-clauses-gfx1250.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hard-clauses-load-monitor.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hard-clauses.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hazard-getreg-waitalu.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazard-kill.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hazard-lds-addtid.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazard-pseudo-machineinstrs.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazard-recognizer-meta-insts.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazard-recognizer-src-shared-base.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazard-shift64.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hazard.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hsa-func-align.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hsa-globals.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hsa-group-segment.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-register-count.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ctor-dtor-list.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v4.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-asan.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v4.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-images.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll (+9-9) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-uniform-workgroup-size-v5.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-wavefrontsize.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-workgroup-processor-mode-v5.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/i8-extract-cost-comparison.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/icmp.i16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/icmp64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll (+1-1) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/global-constant.ll b/llvm/test/CodeGen/AMDGPU/global-constant.ll index 001d80f985a57..c15fced1c8e8a 100644 --- a/llvm/test/CodeGen/AMDGPU/global-constant.ll +++ b/llvm/test/CodeGen/AMDGPU/global-constant.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=GCN,GCN-PAL %s -; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GCN-DEFAULT %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GCN-MESA %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GCN-DEFAULT %s +; RUN: llc -mtriple=amdgpu6.00--amdpal < %s | FileCheck -check-prefixes=GCN,GCN-PAL %s +; RUN: llc -mtriple=amdgpu7.00-- < %s | FileCheck -check-prefixes=GCN,GCN-DEFAULT %s +; RUN: llc -mtriple=amdgpu7.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GCN-MESA %s +; RUN: llc -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefixes=GCN,GCN-DEFAULT %s ; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=R600 %s @private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0] diff --git a/llvm/test/CodeGen/AMDGPU/global-directive.ll b/llvm/test/CodeGen/AMDGPU/global-directive.ll index a55b4f1883e09..8db8e4ff81c42 100644 --- a/llvm/test/CodeGen/AMDGPU/global-directive.ll +++ b/llvm/test/CodeGen/AMDGPU/global-directive.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=SI %s ; Make sure the GlobalDirective isn't merged with the function name diff --git a/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll index f92ba7a8978b9..8af95f193fbb1 100644 --- a/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll +++ b/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-REAL16 %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-REAL16 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s define amdgpu_kernel void @zextload_global_i8_to_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind { ; GFX11-REAL16-LABEL: zextload_global_i8_to_i16: diff --git a/llvm/test/CodeGen/AMDGPU/global-extload-i16.ll b/llvm/test/CodeGen/AMDGPU/global-extload-i16.ll index 97125be0d8345..b8daa65421079 100644 --- a/llvm/test/CodeGen/AMDGPU/global-extload-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/global-extload-i16.ll @@ -1,5 +1,5 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; XUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FIXME: cypress is broken because the bigger testcases spill and it's not implemented diff --git a/llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll b/llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll index d973f7b71fb6d..1cff519c99396 100644 --- a/llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll +++ b/llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefixes=GFX908 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90A %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX1030 %s +; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck -check-prefixes=GFX908 %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck -check-prefixes=GFX90A %s +; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefixes=GFX1030 %s ; Function Attrs: mustprogress nounwind willreturn diff --git a/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll b/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll index 6fe9e1d5561de..3fa6e00380132 100644 --- a/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll +++ b/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN %s +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN %s ; The first load produces address in a VGPR which is used in address calculation ; of the second load (one inside the loop). The value is uniform and the inner diff --git a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll index 29031d81f0289..b69fc139343c9 100644 --- a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll +++ b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GCN-SDAG-FAKE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GCN-GISEL-FAKE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GCN-SDAG-REAL16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GCN-GISEL-REAL16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GCN-SDAG-FAKE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GCN-GISEL-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GCN-SDAG-REAL16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GCN-GISEL-REAL16 %s ; Test S_WAIT_XCNT insertion for global_load/store clauses. ; Introduced additional operations in between the clauses to have the register dependency diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll index 63d63da56080b..75696f6936db2 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12 %s +; RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12 %s ; Test using saddr addressing mode of global_* flat atomic instructions. diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll index 8dff14f1b41a0..ccd3d18b8a782 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu10.30-mesa-mesa3d < %s | FileCheck --check-prefix=GCN %s ; -------------------------------------------------------------------------------- ; amdgcn atomic csub diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll index 84065c4675ab1..b7a1eee608db4 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.08-mesa-mesa3d -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck --check-prefix=GCN %s ; Test using saddr addressing mode of global_* flat atomic instructions. diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll index 58f7c4340276d..c9ebcc1524258 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12 %s +; RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12 %s ; Test using saddr addressing mode of global_* flat atomic instructions. diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll index 15ba43652b80c..3d4b8796b1902 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s +; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s +; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s ; Test using saddr addressing mode of global_*load_* flat instructions. diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll index 1e9fc3d9f447d..b2e6b3831136c 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12 %s +; RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12 %s ; Test using saddr addressing mode of global_*store_* flat instructions. diff --git a/llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll b/llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll index 391ceda2c931b..a9bec174e4d38 100644 --- a/llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll +++ b/llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -memdep-block-scan-limit=1 -amdgpu-scalarize-global-loads < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.03--amdhsa -memdep-block-scan-limit=1 -amdgpu-scalarize-global-loads < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; GCN-LABEL: {{^}}unknown_memdep_analysis: ; GCN: flat_load_dword diff --git a/llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll b/llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll index 6d55e79edbef6..1593ea12d1c66 100644 --- a/llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll +++ b/llvm/test/CodeGen/AMDGPU/global-variable-relocs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.03--amdhsa < %s | FileCheck %s @private = private addrspace(1) global [256 x i32] zeroinitializer @internal = internal addrspace(1) global [256 x i32] zeroinitializer diff --git a/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir b/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir index da1175c02e94a..94c22b1aa8664 100644 --- a/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -start-before=greedy,0 -stop-after=virtregrewriter,0 -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.08-amd-amdhsa -start-before=greedy,0 -stop-after=virtregrewriter,0 -o - %s | FileCheck %s # This testcase used to fail due to introducing a spill of an SGPR # 1024 for every subregister use inside the loop. With overlapping diff --git a/llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir b/llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir index d6a4223a9286a..caa4c87eacc62 100644 --- a/llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir +++ b/llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs -run-pass=greedy -stress-regalloc=2 %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu10.30 -verify-machineinstrs -run-pass=greedy -stress-regalloc=2 %s -o - | FileCheck -check-prefix=GCN %s # Make sure there's no verifier error after register allocation # introduces vreg defs when the MIR parser infers SSA. diff --git a/llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir b/llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir index 1f2e91bc9cc74..a1a64cca78eeb 100644 --- a/llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir +++ b/llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=greedy -verify-machineinstrs -o - %s |FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -run-pass=greedy -verify-machineinstrs -o - %s |FileCheck %s # Testcase is limited to 24 VGPRs. Only a maximum of 6 vreg_128s can # be allocated at the same time. diff --git a/llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir b/llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir index c76a84cb1c5d4..a3523221c7637 100644 --- a/llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir +++ b/llvm/test/CodeGen/AMDGPU/greedy-instruction-split-subrange.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-regalloc -stress-regalloc=3 -start-before=greedy,1 -stop-before=virtregrewriter,1 -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -verify-regalloc -stress-regalloc=3 -start-before=greedy,1 -stop-before=virtregrewriter,1 -o - %s | FileCheck %s --- name: split_instruction_subranges alignment: 1 diff --git a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir index c4ef72416588a..752c335cf34b8 100644 --- a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir +++ b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -greedy-regclass-priority-trumps-globalness=0 -start-before gree... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209118 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
