llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-transforms Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 99.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209120.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/invariant-image-load.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/ipra.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll (+12-12) - (modified) llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/issue130120-eliminate-frame-index.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/issue139317-bad-opsel-reg-sequence-fold.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/issue176966-extend-vector-inreg.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/issue48473.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/itofp.i128.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/kernarg-size.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/kernel-args.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/kill-true-in-return-block.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/known-never-nan.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/known-never-snan.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/large-alloca-graphics.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/large-avgpr-assign-last.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/large-constant-initializer.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/large-phi-search.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-bounds.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx12.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/lds-initializer.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics-gfx1250.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll (+16-16) - (modified) llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-agpr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-callgraph.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-typeid.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll (+9-9) - (modified) llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-addresses-unused.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-mixed-absolute-dynlds.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-no-realign-allocated-variables.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-relocs.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-run-twice.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx1250.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx1250.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.dead.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/licm-regpressure.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/licm-valu.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/licm-wwm.mir (+2-2) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll b/llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll index 70857c9635906..c68f6d63bb0c1 100644 --- a/llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll +++ b/llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1250 < %s | FileCheck %s --check-prefix=GISEL -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1250 < %s | FileCheck %s --check-prefix=DAGISEL -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1250 < %s | FileCheck %s --check-prefix=NRBS +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50--amdpal < %s | FileCheck %s --check-prefix=GISEL +; RUN: llc -global-isel=0 -mtriple=amdgpu12.50--amdpal < %s | FileCheck %s --check-prefix=DAGISEL +; RUN: llc -global-isel=1 -mtriple=amdgpu12.50--amdpal < %s | FileCheck %s --check-prefix=NRBS declare i1 @llvm.amdgcn.s.alloc.vgpr(i32) diff --git a/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll b/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll index 55a5d50f06bbd..cd1dbb35b65d5 100644 --- a/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o - | FileCheck %s +; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa %s -o - | FileCheck %s define amdgpu_kernel void @load_idx_idy(ptr addrspace(4) %disp, ptr %g) { ; CHECK-LABEL: load_idx_idy: diff --git a/llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll b/llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll index bbdf791017247..b7f80675fca18 100644 --- a/llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll +++ b/llvm/test/CodeGen/AMDGPU/invalid-hidden-kernarg-in-kernel-signature.ll @@ -1,7 +1,7 @@ -; RUN: not llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s 2>&1 | FileCheck -check-prefixes=ERROR,GISEL %s -; RUN: not llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s 2>&1 | FileCheck -check-prefix=ERROR %s -; RUN: not llc -global-isel=1 -global-isel-abort=2 -amdgpu-ir-lower-kernel-arguments=0 -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s 2>&1 | FileCheck -check-prefixes=ERROR,GISEL %s -; RUN: not llc -global-isel=0 -amdgpu-ir-lower-kernel-arguments=0 -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.42--amdhsa < %s 2>&1 | FileCheck -check-prefixes=ERROR,GISEL %s +; RUN: not llc -global-isel=0 -mtriple=amdgpu9.42--amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -global-isel=1 -global-isel-abort=2 -amdgpu-ir-lower-kernel-arguments=0 -mtriple=amdgpu9.42--amdhsa < %s 2>&1 | FileCheck -check-prefixes=ERROR,GISEL %s +; RUN: not llc -global-isel=0 -amdgpu-ir-lower-kernel-arguments=0 -mtriple=amdgpu9.42--amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s define amdgpu_kernel void @no_free_sgprs_block_count_x_no_preload_diag(ptr addrspace(1) inreg %out, i512 inreg, i32 inreg "amdgpu-hidden-argument" %_hidden_block_count_x) #0 { ; GISEL: warning: Instruction selection used fallback path for no_free_sgprs_block_count_x_no_preload_diag diff --git a/llvm/test/CodeGen/AMDGPU/invariant-image-load.ll b/llvm/test/CodeGen/AMDGPU/invariant-image-load.ll index 693ebc8ad11ce..4bb6b548cf24e 100644 --- a/llvm/test/CodeGen/AMDGPU/invariant-image-load.ll +++ b/llvm/test/CodeGen/AMDGPU/invariant-image-load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=GFX9 -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=GFX9 +; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s -check-prefix=GFX9 +; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck %s -check-prefix=GFX9 ; Marking the image loads as invariant should allow both loads to be hoisted ; above both stores. diff --git a/llvm/test/CodeGen/AMDGPU/ipra.ll b/llvm/test/CodeGen/AMDGPU/ipra.ll index ec533dae0afd0..c9eb84fae5329 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-ipra < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -enable-ipra < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s ; Kernels are not called, so there is no call preserved mask. ; GCN-LABEL: {{^}}kernel: diff --git a/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll index 2edc78915e0eb..4b6d904cb6e74 100644 --- a/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll +++ b/llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -stop-after=irtranslator < %s | FileCheck %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00--amdpal -stop-after=irtranslator < %s | FileCheck %s define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; CHECK-LABEL: name: basic_test diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll index bd66a07d3da1a..9e32745adc0c9 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1100 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1030 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1100 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1030 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu11.00--amdpal -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu10.30--amdpal -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00--amdpal -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30--amdpal -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s declare amdgpu_cs_chain void @callee(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) declare amdgpu_cs_chain_preserve void @callee_preserve(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll index 0c1d87ac2f8a4..0c5889f986f65 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu11.00--amdpal -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu10.30--amdpal -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00--amdpal -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30--amdpal -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s declare amdgpu_cs_chain void @callee(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) declare amdgpu_cs_chain_preserve void @callee_preserve(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll index 257c63a00d7e5..4a0ac7215806e 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX11 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.30 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.30 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX11 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10 %s ; Test formal argument lowering as well as calls to amdgpu_gfx functions. diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll index f5c7c9122f0af..6e4bcb6e18ff7 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX12 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX12 %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00-amd-amdpal -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX12 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00-amd-amdpal -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX12 %s declare amdgpu_cs_chain void @callee(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) declare amdgpu_cs_chain_preserve void @callee_preserve(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll index 22b87ec313558..74d306b2a77dc 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-TRUE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-FAKE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-TRUE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-FAKE16 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF32,DAGISEL-GFX11-WF32-TRUE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF32,DAGISEL-GFX11-WF32-FAKE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF64,DAGISEL-GFX11-WF64-TRUE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF64,DAGISEL-GFX11-WF64-FAKE16 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10-WF32 %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10-WF64 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-TRUE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-FAKE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-TRUE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-FAKE16 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.30 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s +; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.30 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=GISEL-GFX10 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF32,DAGISEL-GFX11-WF32-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF32,DAGISEL-GFX11-WF32-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF64,DAGISEL-GFX11-WF64-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF64,DAGISEL-GFX11-WF64-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30 -mattr=+wavefrontsize32 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10-WF32 %s +; RUN: llc -global-isel=0 -mtriple=amdgpu10.30 -mattr=+wavefrontsize64 -stop-after=finalize-isel < %s | FileCheck -check-prefix=DAGISEL-GFX10-WF64 %s ; We only care about which physical registers the parameters are copied from; ; the function bodies are just some arbitrary uses. diff --git a/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll index 38e0640873123..af267cac2a1f3 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -stop-after=finalize-isel < %s | FileCheck --check-prefix=DAGISEL %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -stop-after=finalize-isel < %s | FileCheck --check-prefix=GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu12.00--amdpal -stop-after=finalize-isel < %s | FileCheck --check-prefix=DAGISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgpu12.00--amdpal -stop-after=finalize-isel < %s | FileCheck --check-prefix=GISEL %s define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; DAGISEL-LABEL: name: basic_test diff --git a/llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll b/llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll index 1a87887e28d72..20ee7b7fc0819 100644 --- a/llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll +++ b/llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck %s define <4 x float> @issue121601(bfloat %fptrunc) { ; CHECK-L... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209120 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
