llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 124.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209732.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sopc.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir (+7-7) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/known-fpclass-phi.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll (+8-8) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-abs.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir (+1-1) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir index df59855e2d394..3157d4c7fb500 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir @@ -1,10 +1,10 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s -# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX7 %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s +# RUN: llc -mtriple=amdgpu7.01 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX7 %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu11.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s --- name: lshr_i32_ss diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir index 7ef079175c644..b39527ab554a8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir @@ -1,12 +1,12 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX8 %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX8 %s # RUN: FileCheck --check-prefix=ERR %s < %t -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s # RUN: FileCheck --check-prefix=ERR %s < %t -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -run-pass=instruction-select -global-isel-abort=2 -disable-gisel-legality-check -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s # RUN: FileCheck --check-prefix=ERR %s < %t # ERR-NOT: remark diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir index 27be81b8a7e74..47ef62b9fc8e9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir @@ -1,9 +1,9 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s # RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu11.00 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s # RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t # ERR-NOT: remark diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir index 40dd062fc0f39..2766fbe5a309a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX1100 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX1150 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX12 %s +# RUN: llc -mtriple=amdgpu10.30 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu11.00 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX1100 %s +# RUN: llc -mtriple=amdgpu11.50 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX1150 %s +# RUN: llc -mtriple=amdgpu12.00 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX12 %s --- name: mad_u64_u32_vvv diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir index ebd91cfebeb1e..00dd5dcaccd8b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -pass-remarks-missed='gisel*' -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=instruction-select -verify-machineinstrs -pass-remarks-missed='gisel*' -o - %s | FileCheck -check-prefix=GCN %s --- name: test_merge_values_v_s64_v_s32_v_s32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir index fdac9a95cdaf3..deb1636b4b0d2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s --- name: mul_i32_ss diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir index 99ea9b78681f6..16d550d4e1364 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir @@ -1,13 +1,13 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs \ +# RUN: llc -mtriple=amdgpu6.00-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs \ # RUN: -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs \ +# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs \ # RUN: -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32 -run-pass=instruction-select \ +# RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -mattr=+wavefrontsize32 -run-pass=instruction-select \ # RUN: -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=WAVE32,PREGFX11 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -run-pass=instruction-select \ +# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+wavefrontsize32,+real-true16 -run-pass=instruction-select \ # RUN: -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=WAVE32,GFX11-TRUE16 %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -run-pass=instruction-select \ +# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+wavefrontsize32,-real-true16 -run-pass=instruction-select \ # RUN: -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=WAVE32,GFX11-FAKE16 %s --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir index 73cb750390173..5bc889ba29f00 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu11.00 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir index 1ec50261a4549..fd5a3dd0d33c0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu11.00 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir index 01073f3497a14..6e36efdf5093f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu11.00 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir index 2b723340cae35..40e8906f0923b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s --- name: smed3_i32_vvv diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir index 1a2041e927a46..ed14e22d4d93d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir @@ -1,9 +1,9 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-TRUE16 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-FAKE16 %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s +# RUN: llc -mtriple=amdgpu9.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s +# RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-TRUE16 %s +# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-FAKE16 %s --- name: smed3_i16_vvv diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir index 3336367241622..747540255d417 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s --- name: umed3_i32_vvv diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir index 4e355f1b9289e..440bc2b516803 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir @@ -1,9 +1,9 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209732 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
