llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 111.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209733.diff 100 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-splat.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctls.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-poison.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-poison.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-divrem.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir (+6-6) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir index 4e8ab893c96f8..91f3560ad107a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s # Make sure there's no crash if there is somehow no successor block. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir index b54fb5cf2ad64..3147b84a97e34 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s --- name: test_rsq_clamp_flags_ieee_on_f32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir index e20459cd48e87..ea163088b6bcc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir @@ -1,7 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE64 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE64 %s +# RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s --- name: test_wavefrontsize diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir index e57f081f3136b..3c2a32011c24a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -run-pass=legalizer -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu9.0a-mesa-mesa3d -run-pass=legalizer -o - %s | FileCheck -check-prefix=GCN %s --- | define amdgpu_kernel void @test_workitem_id_x_unpacked() "amdgpu-flat-work-group-size"="8192,8192" !reqd_work_group_size !0 { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir index aa198a5c3f4d7..64e5e7a6c1945 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: test_and_s32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir index d2c496e5a349b..5749f6c6c096b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s --- name: test_anyext_s32_to_s64 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir index 65bb2ff1cb2cd..e8b5cda51d457 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir @@ -1,9 +1,9 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=SI %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9PLUS %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9PLUS %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GFX9PLUS %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=SI %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s +# RUN: llc -mtriple=amdgpu9.00-mesa-mesa3d -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9PLUS %s +# RUN: llc -mtriple=amdgpu10.10-mesa-mesa3d -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9PLUS %s +# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefixes=GFX9PLUS %s --- name: test_ashr_s32_s32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir index eafd1e15e2cb3..37f6e330291c7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: test_atomic_cmpxchg_with_success_s32_global diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir index 744e3146d5f15..2bc4b27d93717 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomic_cmpxchg_local_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir index 066e358cdc18e..b76cdb59de356 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_add_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir index 7ec24588abbcc..d066ad7c3a9b7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_and_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir index 802f7f4946ee9..a3fa298e81547 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.08-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.0a-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s # ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_FADD %0:_(p1), %1:_ :: (load store seq_cst (s32), addrspace 1) (in function: atomicrmw_fadd_global_i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir index d8f588ff53c91..615ae6eef8848 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s +# RUN: llc -mtriple=amdgpu7.01-mesa-mesa3d -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel.*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s # ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_FADD %0:_(p3), %1:_ :: (load store seq_cst (s32), addrspace 3) (in function: atomicrmw_fadd_local_i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir index 8aef14b81b4d5..05d5637c72b90 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_max_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir index 24c4bc1e2564f..927f6dead5980 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_min_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir index 743aa503d6070..66a95ab9c99d0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s +# RUN: not llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s # This needs to be expanded into a cmpxchg loop. # TODO: Will AtomicExpand still do this? diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir index 4cf9bea982316..ff54df4b97694 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_or_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir index 8ca6f00629a64..5dce977111e06 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_sub_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir index ff2ac484403a7..c204bdabc3f4c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_umax_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir index ec6f5107d1420..2e3a637be28ab 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_umin_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir index 123580c22fbd3..fc8851493ac41 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -o - %s | FileCheck %s -# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -filetype=null %s 2>&1 | FileCheck -check-prefix=ERROR %s +# RUN: llc -mtriple=amdgpu7.04-mesa-mesa3d -O0 -run-pass=legalizer -o - %s | FileCheck %s +# RUN: not llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer -filetype=null %s 2>&1 | FileCheck -check-prefix=ERROR %s # ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_XCHG %0:_(p0), %1:_ :: (load store seq_cst (s32)) (in function: atomicrmw_xchg_flat_i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir index adb3d7e823369..541d4d458100c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03-mesa-mesa3d -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: atomicrmw_xchg_global_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir index c028a7cb5c44f..abbb76b2837ad 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir +++ b/llv... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209733 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
