llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Mechanically migrate the command-line target spelling on llc/opt RUN lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the redundant -mcpu. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 104.99 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209756.diff 101 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll (+5-5) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll (+2-2) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir index 2cc9ac0ad0a86..3547e5873e3df 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: merge_unmerge @@ -35,7 +35,7 @@ body: | ; CHECK: liveins: $vgpr0_vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 - ; CHECK-NEXT: [[BITCAST:%[a-z]+]]:_(s64) = G_BITCAST [[COPY]](<2 x s32>) + ; CHECK-NEXT: [[BITCAST:%[a-z]+]]:_(s64) = G_BITCAST [[COPY]](<2 x s32>) ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BITCAST]](s64) ; CHECK-NEXT: SI_RETURN implicit $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir index 71431761daabc..0e629d608ef5b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s -# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s +# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s +# RUN: llc -mtriple=amdgpu7.01 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s --- name: test_implicit_def_s32_vgpr_use diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir index bb96cbe676e38..384df19a942f6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s --- name: insert_vector_elt_v4i32_s_s_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir index a868d40df8726..95fb62e125564 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: intrinsic_roundeven_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir index 6318297cc1133..9c2527ccdafaf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: intrinsic_trunc_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir index 72d575e1e5598..a788e7b5e65bc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir @@ -1,7 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: inttoptr_s_p0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir index 1412e314f3a05..19acdc799bce8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir @@ -1,7 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7 -# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12 -# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12 +# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu7.01-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX7 +# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.00-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=GCN,GFX12 +# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgpu12.50-amd-amdhsa -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s -check-prefixes=GCN,GFX12 --- | define amdgpu_kernel void @load_global_v8i32_non_uniform(ptr addrspace(1) %in) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir index 44478f7d7f205..0538f6ee760c3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s --- name: lshr_s32_ss diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir index be25aa92a4348..78aea1e6474a0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir @@ -1,7 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s +# RUN: llc -mtriple=amdgpu9.0a -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s +# RUN: llc -mtriple=amdgpu10.30 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s --- name: mad_u64_u32_sss diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir index f9078a33b139a..cb8aec728d984 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu9.08 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s --- name: merge_s64_s32_s32_ss diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir index e3853281c6762..ff31c66ab88bd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s --- name: uniform_in_vgpr diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir index 97dcd5084cacc..b7387c6d32507 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu10.10 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s --- name: uniform_in_vgpr diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir index 4d48dd9393634..27d5ccbe29ece 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir @@ -1,8 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12 +# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX10 +# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS_GFX12 +# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX10 +# RUN: llc -mtriple=amdgpu12.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS_GFX12 --- name: salu_float diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir index 091d7617198cf..0604cdea14709 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS -# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS +# RUN: llc -mtriple=amdgpu10.10 -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=OLD_RBS +# RUN: llc -mtriple=amdgpu10.10 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s -check-prefixes=NEW_RBS --- name: uniform_in_vgpr diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir index 47fa6d9b960d8..5de0179eb503b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu12.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s --- name: mul_s32_ss diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir index 2f54715ccb8d8..b15c5402e8b2f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: or_s32_ss diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir index 177ae2c70800b..c477c8c41a703 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s --- name: phi_s1_scc_scc_sbranch diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir index 8658afcd1c2f7..4b7b7c29c2d02 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s +# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s +# RUN: llc -mtriple=amdgpu9.08 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s --- name: phi_s32_ss_sbranch diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir index 2e34efd845a14..8ba950e16fb62 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -mtriple=amdgpu12.00 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s --- name: v_s_exp_f32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir index 8643df2b0eeaa..f64b16b53ffd0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s --- name: ptrmask_p1_s_k diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir index de232db6464c2..8541e284c8ddb 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir @@ -1,7 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy |... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209756 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
