https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/209777
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 3e7de3fa2d5f39efb1de272109751bf369514321 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 26 Jun 2026 07:47:18 +0200 Subject: [PATCH] AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (51) Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll | 2 +- llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll | 2 +- llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll | 2 +- llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll | 2 +- llvm/test/CodeGen/AMDGPU/lds-alignment.ll | 2 +- llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll | 2 +- llvm/test/CodeGen/AMDGPU/lds-size.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/liveness.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir | 2 +- llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll | 6 +++--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll | 2 +- .../CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll | 2 +- .../CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll | 2 +- .../AMDGPU/lower-control-flow-live-variables-update.mir | 2 +- .../lower-control-flow-live-variables-update.xfail.mir | 2 +- .../CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll | 2 +- llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/madmk.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir | 2 +- llvm/test/CodeGen/AMDGPU/mem-builtins.ll | 2 +- .../AMDGPU/memory-legalizer-store-infinite-loop.ll | 2 +- llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir | 2 +- llvm/test/CodeGen/AMDGPU/merge-load-store.mir | 2 +- llvm/test/CodeGen/AMDGPU/merge-m0.mir | 2 +- llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir | 2 +- llvm/test/CodeGen/AMDGPU/movrels-bug.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir | 2 +- llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll | 2 +- llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir | 2 +- llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll | 2 +- llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll | 2 +- llvm/test/CodeGen/AMDGPU/nullptr.ll | 2 +- llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir | 2 +- llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll | 2 +- llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 2 +- llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir | 2 +- llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir | 2 +- llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir | 2 +- .../CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir | 2 +- llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll | 2 +- .../AMDGPU/partially-dead-super-register-immediate.ll | 2 +- llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir | 2 +- llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir | 2 +- llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll | 2 +- .../CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/rcp_iflag.ll | 2 +- .../test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll | 2 +- .../test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll | 2 +- llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir | 2 +- llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll | 2 +- llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir | 2 +- llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir | 2 +- .../CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir | 2 +- llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir | 2 +- ...regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir | 2 +- llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir | 2 +- .../regcoalescer-resolve-lane-conflict-by-subranges.mir | 2 +- llvm/test/CodeGen/AMDGPU/register-count-comments.ll | 4 ++-- .../AMDGPU/remaining-virtual-register-operands.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir | 2 +- .../AMDGPU/rename-independent-subregs-mac-operands.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir | 2 +- llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll | 2 +- llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll | 2 +- llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir | 2 +- llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll | 2 +- llvm/test/CodeGen/AMDGPU/select-opt.ll | 2 +- llvm/test/CodeGen/AMDGPU/set-wave-priority.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll | 2 +- llvm/test/CodeGen/AMDGPU/setcc-select.ll | 2 +- llvm/test/CodeGen/AMDGPU/setcc-sext.ll | 2 +- llvm/test/CodeGen/AMDGPU/setcc.ll | 2 +- llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir | 2 +- llvm/test/CodeGen/AMDGPU/sgprcopies.ll | 2 +- llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/si-i1-copies.mir | 2 +- 100 files changed, 132 insertions(+), 132 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll b/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll index 39115568c224f..8c27aff378f91 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll +++ b/llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck %s ; CHECK-LABEL: non_kernel_recursion: define void @non_kernel_recursion(i32 %val) #2 { diff --git a/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll b/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll index 77c14cfcc732a..d2603b76c5ee7 100644 --- a/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope %s +; RUN: llc -mtriple=amdgpu6.00 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope %s ; Although it's modeled without any control flow in order to get better code ; out of the structurizer, @llvm.amdgcn.kill actually ends the thread that calls diff --git a/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll b/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll index ca1346171cb57..ceaa18de60354 100644 --- a/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll +++ b/llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; Check we can compile this test without infinite loop in the ; DAG.computeKnownBits() due to missing (Depth + 1) argument in diff --git a/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll b/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll index a49e5feb59f20..0804da880fb7f 100644 --- a/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll +++ b/llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -O0 -o - %s | FileCheck %s ; CHECK-LABEL: non_uniform_loop ; CHECK: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll index 4d5e2709dc6eb..20a189c5f91f2 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=HSA %s +; RUN: llc -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck -check-prefix=HSA %s @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 16 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 16 diff --git a/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll b/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll index a212ebacf8c2e..3b66ef5d30d68 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; Make sure that m0 is not reinitialized in the loop. diff --git a/llvm/test/CodeGen/AMDGPU/lds-size.ll b/llvm/test/CodeGen/AMDGPU/lds-size.ll index a2471c4c45b7e..bee26bac57ca7 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-size.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-size.ll @@ -1,5 +1,5 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=ALL -check-prefix=EG %s ; This test makes sure we do not double count global values when they are diff --git a/llvm/test/CodeGen/AMDGPU/liveness.mir b/llvm/test/CodeGen/AMDGPU/liveness.mir index a5bf63f555d85..18c6898e33692 100644 --- a/llvm/test/CodeGen/AMDGPU/liveness.mir +++ b/llvm/test/CodeGen/AMDGPU/liveness.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass liveintervals -verify-machineinstrs -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes='print<live-intervals>' -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass liveintervals -verify-machineinstrs -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes='print<live-intervals>' -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s # REQUIRES: asserts # We currently maintain a main liveness range which operates like a superset of # all subregister liveranges. We may need to create additional SSA values at diff --git a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir index ed78b6da798a1..5753f57481c08 100644 --- a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir +++ b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 --run-pass=livevars -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 --run-pass=livevars -o - %s | FileCheck %s --- # Check that super register is defined for an sgpr copy. name: sgpr_copy diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll index 2f3bc3f259e89..2ec3cebd36ae5 100644 --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll @@ -1,10 +1,10 @@ -; RUN: llc -enable-new-pm -mtriple=amdgcn--amdhsa -mcpu=gfx700 -O0 -print-pipeline-passes=tree < %s 2>&1 \ +; RUN: llc -enable-new-pm -mtriple=amdgpu7.00--amdhsa -O0 -print-pipeline-passes=tree < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=GCN-O0 %s -; RUN: llc -enable-new-pm -mtriple=amdgcn--amdhsa -mcpu=gfx700 -print-pipeline-passes=tree < %s 2>&1 \ +; RUN: llc -enable-new-pm -mtriple=amdgpu7.00--amdhsa -print-pipeline-passes=tree < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=GCN-O2 %s -; RUN: llc -O3 -enable-new-pm -mtriple=amdgcn--amdhsa -mcpu=gfx700 -print-pipeline-passes=tree < %s 2>&1 \ +; RUN: llc -O3 -enable-new-pm -mtriple=amdgpu7.00--amdhsa -print-pipeline-passes=tree < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=GCN-O3 %s ; GCN-O0: require<MachineModuleAnalysis> diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll index 9f91d38dd0ead..b22cc75294e5f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -global-isel=0 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-SDAG %s -; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s +; RUN: llc -global-isel=0 -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-SDAG %s +; RUN: llc -global-isel=1 -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-GISEL %s declare i1 @llvm.amdgcn.class.f32(float, i32) #1 declare i1 @llvm.amdgcn.class.f64(double, i32) #1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll index 5e594c5054bc9..4914d0dde51d1 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll @@ -1,5 +1,5 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s declare i64 @llvm.amdgcn.dispatch.id() #1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll index 272b0a2a84938..f4a1817113457 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; XUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; FIXME: Enable for VI. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll index a67ee629f9053..e9151b344b7e4 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=SI %s declare i32 @llvm.amdgcn.workitem.id.x() #1 declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) #1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll index 67592219598f6..462ada162a004 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s declare float @llvm.amdgcn.fdiv.fast(float, float) #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll index 6138701dae22d..3ef45aefd8910 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; ERROR: in function test_kernel{{.*}}: non-hsa intrinsic with hsa target define amdgpu_kernel void @test_kernel(ptr addrspace(1) %out) #1 { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll index 2512fb2774565..ea627732e703f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefix=GCN %s ; FIXME: Requires stack object to not assert ; GCN-LABEL: {{^}}test_ps: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll index c20a44822aee4..7dd71951713bf 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.amdgcn.lds.kernel.id() declare i32 @llvm.amdgcn.workgroup.id.x() diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll index eee0592dc2e2d..17d4293e7e1bb 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_mul_i24: ; GCN: v_mul_i32_i24 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll index 99f5537db2d9b..5c15734b8b31b 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_mul_u24: ; GCN: v_mul_u32_u24 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll index f1fbfebba148c..ec50350ed599b 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s declare float @llvm.amdgcn.rcp.f32(float) #0 declare double @llvm.amdgcn.rcp.f64(double) #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll index c8dfdabed44ff..cf04a66b6229d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare float @llvm.amdgcn.rsq.legacy(float) #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll index 98c3fa9b12b6f..c47334e15911d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s declare i64 @llvm.amdgcn.s.getpc() #0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll index 4a2737535defe..88396740a05e8 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @test_sched_barrier() #0 { ; GCN-LABEL: test_sched_barrier: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll index e24596cb89cd9..19b1b71ede48f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 %s -filetype=obj -filetype=null -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 %s -filetype=obj -filetype=null -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 %s -filetype=obj -filetype=null +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 %s -filetype=obj -filetype=null +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck %s define amdgpu_kernel void @f() { ; CHECK: ; divergent unreachable call void @llvm.amdgcn.unreachable() diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll index 6baf319dc0fbb..bcefb161be44d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}test_wave_barrier: ; GCN-DAG: ; wave barrier diff --git a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll index c90dceeba0611..c3aafd84bd54c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,NOOPT %s -; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,OPT %s +; RUN: llc -O0 -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s +; RUN: llc -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s ; GCN-LABEL: {{^}}test_debug_value: diff --git a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll index 343efc07cd089..8c7dcd9253e8a 100644 --- a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll +++ b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; OBJ: Relocations [ ; OBJ-NEXT: ] diff --git a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir index 54b969bcf252d..32746ef5fce9e 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir +++ b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s # FIXME: update_mir_test_checks tries to incorrectly re-use a variable # name used for a copy, so some of the check variable names were diff --git a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir index c86596ca82e8b..7a6fb07b598bb 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir +++ b/llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgpu7.00-amd-amdhsa -start-before=livevars -stop-after=twoaddressinstruction -verify-machineinstrs -o - %s 2>&1 | FileCheck %s # CHECK: *** Bad machine code: LiveVariables: Block missing from AliveBlocks *** # CHECK-NEXT: function: live_variables_update_block_split_split_def_before_si_end_cf_live_out diff --git a/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll b/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll index d0b8fcf4518af..88609e1cd469a 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn-unknown-unknown -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-unknown-unknown < %s | FileCheck %s ; and can be eliminated ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range: diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir index 4fc50b642e299..289d2463b5b21 100644 --- a/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir +++ b/llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=early-machinelicm -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=early-machinelicm -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=early-machinelicm -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes=early-machinelicm -o - %s | FileCheck %s # Test to check machine LICM does not hoist convergent instructions, # DS_PERMUTE_B32 in this example. diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir index 2cd418f5d7d79..1355789ac4948 100644 --- a/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir +++ b/llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=early-machinelicm -simplify-mir -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=early-machinelicm -simplify-mir -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=early-machinelicm -simplify-mir -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes=early-machinelicm -simplify-mir -o - %s | FileCheck %s # Test to check machine LICM does not hoist convergent instructions, # DS_PERMUTE_B32 in this example. diff --git a/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll b/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll index 50347236bb7ae..66d94b810441b 100644 --- a/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll +++ b/llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s ; If the workgroup id range is restricted, we should be able to use ; mad24 for the usual indexing pattern. diff --git a/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir b/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir index fcc92dcd23b7c..d3eb7ffab67d1 100644 --- a/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir +++ b/llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs -o - %s -debugify-and-strip-all-safe | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass peephole-opt -verify-machineinstrs -o - %s -debugify-and-strip-all-safe | FileCheck -check-prefix=GCN %s # GCN-LABEL: bb.0: # GCN: S_MOV_B32 1082130432 diff --git a/llvm/test/CodeGen/AMDGPU/madmk.ll b/llvm/test/CodeGen/AMDGPU/madmk.ll index 720b9834ea974..182e638bd65a9 100644 --- a/llvm/test/CodeGen/AMDGPU/madmk.ll +++ b/llvm/test/CodeGen/AMDGPU/madmk.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; XUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; FIXME: None of these trigger madmk emission anymore. It is still ; possible, but requires the correct registers to be used which is diff --git a/llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir b/llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir index d65a3b888a675..a19c01dfb8ce4 100644 --- a/llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir +++ b/llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=machine-cp -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=machine-cp -o - %s | FileCheck %s # machine copy prop should not introduce use before def --- diff --git a/llvm/test/CodeGen/AMDGPU/mem-builtins.ll b/llvm/test/CodeGen/AMDGPU/mem-builtins.ll index ba09608d61446..65cb6f9fce994 100644 --- a/llvm/test/CodeGen/AMDGPU/mem-builtins.ll +++ b/llvm/test/CodeGen/AMDGPU/mem-builtins.ll @@ -1,5 +1,5 @@ ; RUN: not llc -mtriple=r600 < %s 2>&1 | FileCheck -check-prefix=ERROR %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s declare hidden i32 @memcmp(ptr addrspace(1) readonly nocapture, ptr addrspace(1) readonly nocapture, i64) #0 declare hidden ptr addrspace(1) @memchr(ptr addrspace(1) readonly nocapture, i32, i64) #1 diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll index a718b6630846c..c40571e5c0691 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN %s ; Effectively, check that the compile finishes; in the case ; of an infinite loop, llc toggles between merging 2 ST4s diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir index 68e9302ff2a57..c231a6c0478ef 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s # Check that SILoadStoreOptimizer honors physregs defs/uses between moved # instructions. diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir index bd2b783d20e52..9f7a053222766 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s # Check that SILoadStoreOptimizer honors memory dependencies between moved # instructions. diff --git a/llvm/test/CodeGen/AMDGPU/merge-m0.mir b/llvm/test/CodeGen/AMDGPU/merge-m0.mir index 721e69320dcb3..a06ffafa7a046 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-m0.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-m0.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: merge-m0-many-init # GCN: bb.0.entry: diff --git a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir index 60caecc0d47ee..791adc4e5cacd 100644 --- a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir +++ b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=prolog-epilog -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=prolog-epilog -o - %s | FileCheck %s # Make sure the MIR printer doesn't crash when there are dead frame indexes. The # CSR SGPR frame indexes are inserted, but deleted. diff --git a/llvm/test/CodeGen/AMDGPU/movrels-bug.mir b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir index 4ec56fbe28024..5f4ae227e3404 100644 --- a/llvm/test/CodeGen/AMDGPU/movrels-bug.mir +++ b/llvm/test/CodeGen/AMDGPU/movrels-bug.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=post-RA-sched %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes=post-RA-sched %s -o - | FileCheck %s # This tests a situation where a sub-register of a killed super-register operand # of V_MOVRELS happens to have an undef use later on. This leads to the post RA diff --git a/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir b/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir index 03e1b3a0d2caf..b0e0c0ffd154e 100644 --- a/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir +++ b/llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 \ +# RUN: llc -mtriple=amdgpu6.00 \ # RUN: "-passes=require<amdgpu-resource-usage>,invalidate<amdgpu-resource-usage>" \ # RUN: --print-pipeline-passes --filetype=null %s | FileCheck %s diff --git a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll index 824264dfd61a4..8d1451e1a7128 100644 --- a/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll +++ b/llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 -O0 -filetype=null < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=amdgpu7.00-unknown-amdhsa -O0 -filetype=null < %s 2>&1 | FileCheck %s @I = global i32 42 @P = global ptr @I diff --git a/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir index 2e683b53818c3..27a941602eca9 100644 --- a/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir +++ b/llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass register-coalescer -o - %s | FileCheck %s # Check that coalescer may create wider register tuple than in source. --- diff --git a/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll b/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll index 3de4d29cd21ba..19c0f1a473998 100644 --- a/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll +++ b/llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll index faf4b4077cc47..ee9150ddf3553 100644 --- a/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll +++ b/llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll @@ -1,6 +1,6 @@ ; XFAIL: * ; REQUIRES: asserts -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 < %s +; RUN: llc -mtriple=amdgpu6.00-- < %s ; This is a temporary xfail, as the assembly printer is broken when dealing with ; lowerConstant() trying to return a value of size greater than 8 bytes. diff --git a/llvm/test/CodeGen/AMDGPU/nullptr.ll b/llvm/test/CodeGen/AMDGPU/nullptr.ll index 79c11fb2a7c37..da74ad5d5fda8 100644 --- a/llvm/test/CodeGen/AMDGPU/nullptr.ll +++ b/llvm/test/CodeGen/AMDGPU/nullptr.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx600 | FileCheck -check-prefixes=CHECK,GCN %s +;RUN: llc < %s -mtriple=amdgpu6.00-- | FileCheck -check-prefixes=CHECK,GCN %s ;RUN: llc < %s -mtriple=r600-- | FileCheck -check-prefixes=CHECK,R600 %s %struct.S = type { ptr addrspace(5), ptr addrspace(1), ptr addrspace(4), ptr addrspace(3), ptr, ptr addrspace(2)} diff --git a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir index c721b747a5c5a..fa4b2b59b5c89 100644 --- a/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir +++ b/llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-fold-operands -mattr=+dx10-clamp-and-ieee-mode %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-fold-operands -mattr=+dx10-clamp-and-ieee-mode %s -o - | FileCheck -check-prefix=GCN %s --- diff --git a/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll b/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll index fde295ef61f41..cade1d6d27f53 100644 --- a/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll +++ b/llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck --check-prefix=SI %s +; RUN: llc < %s -mtriple=amdgpu6.00 | FileCheck --check-prefix=SI %s ; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s ; Make sure the OpenCL Image lowering pass doesn't crash when argument metadata diff --git a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir index 7626732ecb4bf..d6e78801cf40a 100644 --- a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # Check that constant is in SGPR registers diff --git a/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir b/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir index f8128cbe3e53d..7ea614f5a6e2c 100644 --- a/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir +++ b/llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass si-optimize-exec-masking-pre-ra -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s +# RUN: llc -run-pass si-optimize-exec-masking-pre-ra -mtriple=amdgpu6.00 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s --- # GCN-LABEL: name: opt_exec_copy_fold # GCN: %2:vreg_64 = COPY $exec diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir index c5e54eac6aed8..1280f015358fe 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -run-pass=si-optimize-exec-masking-pre-ra -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=si-optimize-exec-masking-pre-ra -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s # Check for regression from assuming an instruction was a copy after # dropping the opcode check. diff --git a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir index efe1ca91fb29c..f7e9e248c7698 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-optimize-exec-masking -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-optimize-exec-masking -o - %s | FileCheck %s --- | define amdgpu_kernel void @optimize_if_and_saveexec_xor(i32 %z, i32 %v) { diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir index 549668130236c..539523ca034e9 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s # GCN: name: negated_cond_vop2 # GCN: %0:sreg_64_xexec = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll index f9678b966d805..2e3b1c61a4dc4 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll +++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @negated_cond(ptr addrspace(1) %arg1) { ; GCN-LABEL: negated_cond: diff --git a/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll b/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll index 92a8a18a9aede..6dc11f28313b3 100644 --- a/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll +++ b/llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-coalescing < %s +; RUN: llc -mtriple=amdgpu6.00 -verify-coalescing < %s ; The original and requires materializing a 64-bit immediate for ; s_and_b64. This is split into 2 x v_and_i32, part of the immediate diff --git a/llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir b/llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir index 2eed55c01a90e..ddb38d336a9ca 100644 --- a/llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir +++ b/llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # Check that when we jump through several subregisters in sequence of # reg_sequence we can still find a plain src for a copy. diff --git a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir index 4589d92a53144..e08b915ed81c0 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s # The wrong form of scavengeRegister was used, so it wasn't accounting # for the iterator passed to eliminateFrameIndex. It was instead using diff --git a/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll b/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll index 8cd62abf518fd..28fcc8d707647 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll +++ b/llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -O3 -mtriple=amdgpu6.00 < %s | FileCheck --check-prefix=CHECK %s ; SIInsertWaitcnts should preserve waitcnt instructions coming from the user diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll index 1e9a4e83b510b..ce55d65071e94 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+max-private-element-size-4 < %s | FileCheck -check-prefix=GCN %s ; Pointer value is stored in a candidate for LDS usage. diff --git a/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll b/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll index 67c796029cbf3..408f972e952a0 100644 --- a/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll +++ b/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck --check-prefix=GCN %s define amdgpu_kernel void @rcp_uint(ptr addrspace(1) %in, ptr addrspace(1) %out) #0 { ; GCN-LABEL: rcp_uint: diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll index 9a6f0eadc1a06..c41e731d768ae 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=amdgpu6.00 < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "exec". diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll index 52fd8e4faebfd..b91c94fce1a22 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=amdgpu6.00 < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "m0". diff --git a/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir b/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir index bce9c0d96f3e5..f213bcded91fa 100644 --- a/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir +++ b/llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-optimize-exec-masking %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-optimize-exec-masking %s -o - | FileCheck -check-prefix=GCN %s --- # GCN-LABEL: name: reduce_and_saveexec diff --git a/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll b/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll index 75d774df4c7dd..f40fad7ae66fd 100644 --- a/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll +++ b/llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4: ; GCN: s_load_dwordx2 diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir index 7f2fd9ac74fa9..4c46949884c9b 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s # REQUIRES: asserts # # This test will provoke a Couldn't join subrange unreachable without the diff --git a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir index bddb8224c8228..06ba87dd7653a 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass register-coalescer -o - %s | FileCheck --check-prefix=GCN %s # # See bug http://llvm.org/PR33524 for details of the problem being checked here # This test will provoke a subrange join (see annotations below) during register coalescing diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir index f36720beca4a7..6545da849fefc 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s --- name: couldnt_join_subrange_implicit_def_pred_block diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir index 4e7b49d898d02..8d54e20547f1f 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass register-coalescer -o - %s | FileCheck %s # Test that register coalescing does not allow a call to # LIS->getInstructionIndex with a DBG_VALUE instruction, which does not have diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir index 4be94f7599948..ac70f17faaee5 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s # Bug 39602: Avoid "Couldn't join subrange" error when clearing valid # lanes on an implicit_def that later cannot be erased. diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir index 999d07146d563..da47298e0ba1f 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -mcpu=gfx700 -run-pass=register-coalescer | FileCheck %s +# RUN: llc -o - %s -mtriple=amdgpu7.00-amd-amdhsa-opencl -run-pass=register-coalescer | FileCheck %s --- # Checks for a bug where subregister liveranges were not properly pruned for # an IMPLCITI_DEF that gets removed completely. diff --git a/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir b/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir index b77aae761b2fb..31d86cd43ee5d 100644 --- a/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir +++ b/llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s # diff --git a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll index b6664f2cc1030..6a14ec9a03536 100644 --- a/llvm/test/CodeGen/AMDGPU/register-count-comments.ll +++ b/llvm/test/CodeGen/AMDGPU/register-count-comments.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -asm-verbose < %s | FileCheck -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 -asm-verbose < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu7.00-unknown-amdhsa -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 diff --git a/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir b/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir index 2613f7d8757a1..3476342177d5e 100644 --- a/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir +++ b/llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -start-before=greedy,2 -filetype=null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -verify-machineinstrs -start-before=greedy,2 -filetype=null %s 2>&1 | FileCheck %s # This testcase fails register allocation at the same time it performs # virtual register splitting (by introducing VGPR to AGPR copies). We @@ -18,7 +18,7 @@ ret void } - attributes #0 = { "amdgpu-waves-per-eu"="10,10" "target-cpu"="gfx908" } + attributes #0 = { "amdgpu-waves-per-eu"="10,10" } ... --- diff --git a/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir b/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir index 287f61b7321d7..29373f9df5d30 100644 --- a/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir +++ b/llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -start-before=greedy -stop-after=virtregrewriter -stress-regalloc=3 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -start-before=greedy -stop-after=virtregrewriter -stress-regalloc=3 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # Check that subreg use is live at the point of materialization, not just the main range. # Do not rematerialize if used subreg is dead at a new index. diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir index 570ff239f0609..5357ab970ba29 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -passes=register-coalescer,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s --- # GCN-LABEL: name: mac_invalid_operands diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir index 94a8ad022b295..4f8c7e785341e 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass register-coalescer,rename-independent-subregs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass register-coalescer,rename-independent-subregs -o - %s | FileCheck %s --- | define amdgpu_kernel void @test0() { ret void } define amdgpu_kernel void @test1() { ret void } diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir index 28a58b8201be5..8eb8050dbd9f2 100644 --- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir +++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s --- | define void @test_vreg_96_w64() !dbg !5 { entry: diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir index 86877696b9458..8c6e4c400b44a 100644 --- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir +++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s --- name: test_subregs_composition_vreg_1024 tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir index 90b0430d82d66..67c5797c872fa 100644 --- a/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir +++ b/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s --- name: test_subregs_composition_vreg_1024 tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll b/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll index b80d7377b8a55..b6d40afd681d5 100644 --- a/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll +++ b/llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s -debug-only=igrouplp 2>&1 | FileCheck --check-prefixes=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s -debug-only=igrouplp 2>&1 | FileCheck --check-prefixes=GCN %s diff --git a/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll b/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll index b610a38e321b6..1ca59c25d64f4 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll +++ b/llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; FIXME: This currently doesn't do a great job of clustering the ; loads, which end up with extra moves between them. Right now, it diff --git a/llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir b/llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir index d758bbc80c95a..d398901ff939b 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx700 -run-pass machine-scheduler -verify-machineinstrs %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00 -run-pass machine-scheduler -verify-machineinstrs %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: SU(0): $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir index 0859e2fe98dc0..281196c6616b4 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -misched-regpressure=false -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=NORP +# RUN: llc -mtriple=amdgpu6.00 -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -misched-regpressure=false -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=NORP # REQUIRES: asserts diff --git a/llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll b/llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll index 32c89bbd4ca01..dddf5cbddf1d6 100644 --- a/llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll +++ b/llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -o - %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -o - %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone declare i32 @llvm.amdgcn.sffbh.i32(i32) nounwind readnone speculatable diff --git a/llvm/test/CodeGen/AMDGPU/select-opt.ll b/llvm/test/CodeGen/AMDGPU/select-opt.ll index 84bedb0e7158f..83eb86c075e6c 100644 --- a/llvm/test/CodeGen/AMDGPU/select-opt.ll +++ b/llvm/test/CodeGen/AMDGPU/select-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; Make sure to test with f32 and i32 compares. If we have to use float ; compares, we always have multiple condition registers. If we can do diff --git a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll index 9c817b6f009f0..d1958e2957df3 100644 --- a/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll +++ b/llvm/test/CodeGen/AMDGPU/set-wave-priority.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-set-wave-priority=true -o - %s | \ +; RUN: llc -mtriple=amdgpu6.00 -amdgpu-set-wave-priority=true -o - %s | \ ; RUN: FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -stop-after=si-late-branch-lowering -o - %s | \ -; RUN: llc -x mir -mtriple=amdgcn -mcpu=gfx600 -passes=amdgpu-set-wave-priority -o - | \ -; RUN: llc -x mir -mtriple=amdgcn -mcpu=gfx600 -start-after=si-late-branch-lowering -o - | \ +; RUN: llc -mtriple=amdgpu6.00 -stop-after=si-late-branch-lowering -o - %s | \ +; RUN: llc -x mir -mtriple=amdgpu6.00 -passes=amdgpu-set-wave-priority -o - | \ +; RUN: llc -x mir -mtriple=amdgpu6.00 -start-after=si-late-branch-lowering -o - | \ ; RUN: FileCheck %s ; CHECK-LABEL: no_setprio: diff --git a/llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll b/llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll index c2a38e44c8bc2..8989cbe6a1cb8 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck %s define i32 @select.hi32.sgpr.eq(i64 inreg %mask, i32 inreg %a, i32 inreg %b) { ; CHECK-LABEL: select.hi32.sgpr.eq: diff --git a/llvm/test/CodeGen/AMDGPU/setcc-select.ll b/llvm/test/CodeGen/AMDGPU/setcc-select.ll index 9fa246632b79f..8f65c020b92d6 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc-select.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc-select.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck %s define i32 @select.hi32.sgpr.ult(i64 inreg %mask, i32 inreg %a, i32 inreg %b) { ; CHECK-LABEL: select.hi32.sgpr.ult: diff --git a/llvm/test/CodeGen/AMDGPU/setcc-sext.ll b/llvm/test/CodeGen/AMDGPU/setcc-sext.ll index bc3730e4be872..6da8fd4dd1c39 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc-sext.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc-sext.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}setcc_sgt_true_sext: ; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}} diff --git a/llvm/test/CodeGen/AMDGPU/setcc.ll b/llvm/test/CodeGen/AMDGPU/setcc.ll index 70cd81aafd261..575b128b1f3af 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00-- < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -mtriple=r600-- -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir index 884125772b955..2b795daf812e7 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - %s | FileCheck -check-prefixes=SHARE,GCN %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -no-stack-slot-sharing -o - %s | FileCheck -check-prefixes=NOSHARE,GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - %s | FileCheck -check-prefixes=SHARE,GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -run-pass=greedy,virtregrewriter,stack-slot-coloring -no-stack-slot-sharing -o - %s | FileCheck -check-prefixes=NOSHARE,GCN %s # -run-pass is used to artifically avoid using split register allocation, which would avoid stressing StackSlotColoring. diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir b/llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir index 34bf123d58cc1..600e8d1162413 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s --- name: copy_to_vreg_1 diff --git a/llvm/test/CodeGen/AMDGPU/sgprcopies.ll b/llvm/test/CodeGen/AMDGPU/sgprcopies.ll index 1a349c8d99c82..e4ab62a03eda8 100644 --- a/llvm/test/CodeGen/AMDGPU/sgprcopies.ll +++ b/llvm/test/CodeGen/AMDGPU/sgprcopies.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck -check-prefix=GCN %s +; RUN: llc < %s -mtriple=amdgpu6.00 | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}checkTwoBlocksWithUniformBranch ; GCN: BB0_2 diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir index c474ec53fc65c..45fff519d94e8 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir +++ b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir @@ -1,5 +1,5 @@ -# RUN: llc -verify-machineinstrs -mtriple=amdgcn -mcpu=gfx600 -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -verify-machineinstrs -mtriple=amdgcn -mcpu=gfx600 -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu6.00 -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu6.00 -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s # Check that add with carry out isn't incorrectly reduced to e32 when # the carry out is a virtual register. diff --git a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir index bad989832b4f0..b73cbf2c386a2 100644 --- a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu6.00 -passes=si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/si-i1-copies.mir b/llvm/test/CodeGen/AMDGPU/si-i1-copies.mir index 0dc8e1f9fd562..6892afba6ee28 100644 --- a/llvm/test/CodeGen/AMDGPU/si-i1-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/si-i1-copies.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=si-i1-copies -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=si-i1-copies -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s # Test that the new IMPLICIT_DEF is inserted in the correct location. --- _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
