https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/209779
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 8519b9255c412a9317c1b0e96f361bb07289173c Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 26 Jun 2026 07:47:35 +0200 Subject: [PATCH] AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (53) Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir | 2 +- .../GlobalISel/combine-shift-imm-chain-illegal-types.mir | 2 +- .../AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir | 2 +- .../test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll | 2 +- .../GlobalISel/combine-shift-of-shifted-logic-shlsat.mir | 2 +- .../AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll | 2 +- .../GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll | 2 +- .../AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll | 2 +- .../GlobalISel/irtranslator-readnone-intrinsic-callsite.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll | 2 +- .../GlobalISel/irtranslator-struct-return-intrinsics.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir | 2 +- .../AMDGPU/GlobalISel/legalize-extractelement-crash.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir | 2 +- .../AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir | 2 +- .../AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir | 2 +- .../AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll | 2 +- .../AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir | 2 +- .../AMDGPU/GlobalISel/postlegalizercombiner-select.mir | 2 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll | 4 ++-- .../AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll | 4 ++-- .../GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll | 2 +- .../GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll | 4 ++-- .../GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll | 2 +- .../GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll | 4 ++-- .../regbankselect-amdgcn.struct.ptr.buffer.store.ll | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir | 2 +- llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll | 4 ++-- llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 4 ++-- 93 files changed, 109 insertions(+), 109 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir index 2c7478fee8ebc..3a879aa6cef8f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: add_nullptr_shl_add diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir index 07010b206f4da..103b0aa6a6d31 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: narrow_ashr_s64_32_s64amt diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir index 55094eae07e0c..c595f8b085739 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s # Tries to emit a foldable G_PTR_ADD with (p1, s32) operands. --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir index 83e4e9204b9cf..df67eca5ef0ee 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_f16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir index a00ae041de05c..9729a23c816c3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_fcanonicalize diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir index 51084d6906e04..81309a552e3b2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: fshl_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir index fac9729e8f029..a27a231d8dce2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_f16_poszero_nsz diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir index 9a5c69cb92a70..5d513504f71ce 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: uitofp_char_to_f32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir index fd407bdbac315..2ed0b06d39fea 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: narrow_lshr_s64_32_s64amt diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir index b743b5e9f3026..e75a811c0bee6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_const_const_1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir index 47fedd53a9c31..f684f2c0f3a8f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_const_const diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir index 6ece1c4ad300c..574cebabac436 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_add_rhs diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir index 48f90922505c8..ebb6f495ce5a2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: rotl_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir index c4f94d42c102f..5b4e5853be124 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s --- name: lshr_zext_i16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir index 7d217362a98da..fdd7f9ac22391 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_ashr_i44 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir index 3b1615a8034a9..e0ded9472f0f0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: sshlsat_1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll index 5a68b2d83a607..65208a2d68c0d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 < %s | FileCheck %s define amdgpu_cs i32 @test_shl_1(i32 inreg %arg1) { ; CHECK-LABEL: test_shl_1: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir index a1af7df2f5a56..2c5ca1f79c7ee 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: ushlsat_and_1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll index a7bb0b32f9dc1..98de0a416e5b9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 < %s | FileCheck %s define amdgpu_cs i32 @test_shl_and_1(i32 inreg %arg1) { ; CHECK-LABEL: test_shl_and_1: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir index f122a774f9a57..2b5fec02bdb24 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s --- name: combine_ashr diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir index 6423bea288591..27ff19aaeff06 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir index 7f2e04e11027b..0d89e8b18ad19 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: trunc_s32_shl_s64_5 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll index f977f0ce373c4..9df2b588c9429 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -amdgpu-enable-remove-incompatible-functions=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=legalizer -o - %s | FileCheck %s +; RUN: llc -global-isel -amdgpu-enable-remove-incompatible-functions=0 -mtriple=amdgpu7.00-amd-amdhsa -stop-after=legalizer -o - %s | FileCheck %s ; Make sure legalizer info doesn't assert on dummy targets diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir index c91b2b90c6053..36b485be33048 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir index 5bc1309914e8b..a9c5c6c03b542 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN --- name: test_sendmsg diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir index db7b855965ce0..4102f0e5423b8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir index 3a948b8843997..d3bb2553a1675 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir index bfb8d88170518..cbcd59289fcc3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir index d0531fb0e955a..e8c020e028735 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir index a36bae4a6d289..c36173c927977 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2> %t | FileCheck -check-prefixes=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2> %t | FileCheck -check-prefixes=GCN %s # RUN: FileCheck -check-prefix=ERR %s < %t # ERR-NOT: remark: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir index d9505d838baba..03416abb4117e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir index 76b21e92903a2..0f5397ce0fb0a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN --- name: g_phi_s32_ss_sbranch diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir index a1c35ae7401d2..e9eae5dceb3d3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir index 18af60d754fb8..322dc543c41f0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir index 1b3184a642477..1706beb5bb46e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN +# RUN: llc -mtriple=amdgpu6.00 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll index b6703e59d9605..099c8e1bc0416 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 -stop-after=irtranslator -global-isel %s -o - | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -O0 -stop-after=irtranslator -global-isel %s -o - | FileCheck %s declare void @llvm.amdgcn.s.sendmsg(i32 immarg, i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll index 9b3799d69a6f1..5614e7d422b00 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=irtranslator -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck %s @var = global i32 poison diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll index 3a3dfd4a3b0ae..6961a876a5ca3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -stop-after=irtranslator %s -o - | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -stop-after=irtranslator %s -o - | FileCheck %s define float @v_constained_fadd_f32_fpexcept_strict(float %x, float %y) #0 { ; CHECK-LABEL: name: v_constained_fadd_f32_fpexcept_strict diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll index 446c9aba2f19e..2d60999ff8773 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=irtranslator < %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator < %s | FileCheck %s define amdgpu_kernel void @system_one_as_acquire() { ; CHECK-LABEL: name: system_one_as_acquire diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll index 9ed96d5968855..0feb2d76f0074 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=irtranslator -o - %s | FileCheck --check-prefix=FIXED %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck --check-prefix=FIXED %s ; Make sure arg1 is not allocated in v31, which is reserved for ; workitem IDs with -amdgpu-fixed-function-abi. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll index 8538c8b42be80..524d9ea5a423d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=irtranslator -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator -o - %s | FileCheck %s ; Test 64-bit pointer with 64-bit index define <2 x ptr addrspace(1)> @vector_gep_v2p1_index_v2i64(<2 x ptr addrspace(1)> %ptr, <2 x i64> %idx) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll index d0c9430a1e467..418ca159196e0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -simplify-mir -global-isel -mtriple=amdgcn -mcpu=gfx600 -stop-after=irtranslator %s -o - | FileCheck %s +; RUN: llc -simplify-mir -global-isel -mtriple=amdgpu6.00 -stop-after=irtranslator %s -o - | FileCheck %s ; Check the flags set on the memory operands for loads determined to ; be constants by alias analysis. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll index 719f462970894..46498710bafc9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -O0 -stop-after=irtranslator %s -o - | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -O0 -stop-after=irtranslator %s -o - | FileCheck %s ; Size operand should be the minimum of the two pointer sizes. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll index 1101471f9fee9..3629f6361ed03 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -stop-after=irtranslator < %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -stop-after=irtranslator < %s | FileCheck %s define void @prefetch_read(ptr %ptr) { ; CHECK-LABEL: name: prefetch_read diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll index f50bdcb70d8d1..31da8e7c7179d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=irtranslator < %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -stop-after=irtranslator < %s | FileCheck %s define ptr @ptrmask_flat_i64(ptr %ptr, i64 %mask) { ; CHECK-LABEL: name: ptrmask_flat_i64 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll index 8602bd2b02bce..3e05ed51ea1bf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -global-isel -stop-after=irtranslator -o - %s | FileCheck %s ; Make sure that an intrinsic declaration that has side effects, but ; called with a readnone call site is translated to diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll index 23ceb1533c38a..55b4188ddbda0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s define i16 @uaddsat_i16(i16 %lhs, i16 %rhs) { ; CHECK-LABEL: name: uaddsat_i16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll index eeb1f55a88e68..ad3424e82475f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -global-isel -stop-after=irtranslator -o - %s | FileCheck %s declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll index 955ed34a343d7..27dd893b68386 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 -stop-after=irtranslator -global-isel %s -o - | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -O0 -stop-after=irtranslator -global-isel %s -o - | FileCheck %s define i8 @f_i1_1() { ; CHECK-LABEL: name: f_i1_1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir index 5e288bb011d59..ee09bcd239b60 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s ## Check that we don't incorrectly assume known zeroes for and extend of a truncated ptrtoint ## Test case for https://github.com/llvm/llvm-project/issues/139598 --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir index a86cb34ca3846..ec765ff67f852 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -O0 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -O0 -run-pass=legalizer %s -o - | FileCheck %s --- name: legal_v2s32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir index b0bfcdaf1eccc..d5af0a484b8b5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s --- name: f diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir index dcfc8b0f2ae2d..96b3b11d2080c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s --- name: test_insert_s64_s32_offset0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir index 462e33a7fc44a..59eeefd8e01b9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s --- name: test_amdgcn_fdiv_fast diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir index 91b13a6d3ed72..3d7bac8a8268e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 -run-pass=legalizer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -O0 -run-pass=legalizer -o - %s | FileCheck %s --- name: test_inttoptr_s64_to_p0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir index 0b218e41950dd..828b3cf7b45b5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: not llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=legalizer -filetype=null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=amdgpu6.00 -run-pass=legalizer -filetype=null %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: unable to legalize instruction: %3:_(p0) = G_JUMP_TABLE %jump-table.0 (in function: jt_test) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir index 2488dbd96382e..4c5d4fb54dca3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s --- name: memcpy_test diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir index 92e6716b69b3b..ac03b0fafb632 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s --- name: memcpyinline_test diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir index eeac99bfa0935..589c84857cd73 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s --- name: memmove_test diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir index 9b9fe9f6b5113..5986b86fea95f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s --- name: memset_test diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir index 98596aff12328..287e2b3655b4a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -run-pass=legalizer -verify-machineinstrs -o - %s | FileCheck %s --- name: memsetinline_test diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir index 1457e50eccbb2..f53afb122d50f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -O0 -run-pass=legalizer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -O0 -run-pass=legalizer -o - %s | FileCheck %s --- name: test_merge_s32_s32_s64 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir index 7e55f92f8c907..bfc53d8221a76 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck %s --- name: test_ptrtoint_p0_to_s64 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir index fb9c18b965209..fe77f2efa7f82 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck %s --- name: test_unmerge_s32_s64 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll index 59782dace76c7..6f2c12a9733bd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll @@ -1,4 +1,4 @@ -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefix=GCN %s ; FIXME: Dropped parts from original test diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll index c543f5f9bda09..af07cee21a2a2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=GCN %s declare void @llvm.memcpy.inline.p1.p1.i32(ptr addrspace(1), ptr addrspace(1), i32, i1 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll index 311c691b907b5..84bdcdeb1ec46 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx600 -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=35 %s -o - | FileCheck -check-prefix=LOOP %s -; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx600 -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=37 %s -o - | FileCheck -check-prefix=UNROLL %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-- -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=35 %s -o - | FileCheck -check-prefix=LOOP %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-- -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=37 %s -o - | FileCheck -check-prefix=UNROLL %s declare void @llvm.memcpy.p1.p1.i32(ptr addrspace(1), ptr addrspace(1), i32, i1 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll index 1169c1bbbc60c..2c3c16fd5a306 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx600 -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s -; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx600 -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-- -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-- -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s declare void @llvm.memmove.p1.p1.i32(ptr addrspace(1), ptr addrspace(1), i32, i1) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll index 687c0d1a90ff2..a2186a2d9670b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=GCN %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=GCN %s declare void @llvm.memset.inline.p1.i32(ptr addrspace(1), i8, i32, i1 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll index 0a01248d713e3..576d1f8b521a5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-- -mcpu=gfx600 -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=35 %s -o - | FileCheck -check-prefix=LOOP %s -; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=gfx600 -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=37 %s -o - | FileCheck -check-prefix=UNROLL %s +; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu6.00-- -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=35 %s -o - | FileCheck -check-prefix=LOOP %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-- -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=37 %s -o - | FileCheck -check-prefix=UNROLL %s declare void @llvm.memset.p1.i32(ptr addrspace(1), i8, i32, i1) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll index 4e931246c101a..e2f004b90e469 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx600 -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 -o - %s | FileCheck %s define amdgpu_cs void @test1(i32 %arg1, <4 x i32> inreg %arg2, i32, ptr addrspace(6) inreg %arg3) { ; CHECK-LABEL: test1: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll index 4203821d7a35e..d8693a6e4afcf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx700 < %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-unknown-amdhsa < %s | FileCheck %s declare i32 @llvm.umin.i32(i32, i32) declare i32 @llvm.umax.i32(i32, i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir index f6071c18f9178..42b2001d4ce93 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s --- name: test_reassoc_infinite_loop diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir index f007e0cb57044..a425273490805 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s --- name: select_from_different_results_of_unmerge_values diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll index 2bab907079634..4ad8eb432c676 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s ; Natural mapping define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll index 8c97df7d0e4fb..5468f2462876b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s ; Natural mapping define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll index cb20081e3e1ec..931d066099396 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s ; Natural mapping define amdgpu_ps float @raw_ptr_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll index f620b91e623fd..d327372fc7c86 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s ; Natural mapping define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll index 98872c5e1df52..8ca6f705fac04 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s ; Natural mapping define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll index 615d7c15cbb8b..4d18cfc3966d6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-fast -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -regbankselect-greedy -o - %s | FileCheck %s ; Natural mapping define amdgpu_ps float @struct_ptr_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll index 27143beed85ef..b16965c55f843 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=amdgpu-regbanklegalize -o - %s | FileCheck %s ; Natural mapping define amdgpu_ps void @struct_ptr_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir index 0c32319a04837..d4dd6647d6647 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s --- name: fabs_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir index d12235a3c3064..2fce2409e38b0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -verify-machineinstrs -o - | FileCheck %s --- name: fneg_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir index bdddc371de0c9..512eeeb65eb0f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir @@ -1,5 +1,5 @@ -# RUN: not llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=regbankselect -regbankselect-fast -filetype=null %s 2>&1 | FileCheck %s -# RUN: not llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=regbankselect -regbankselect-greedy -filetype=null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=amdgpu6.00 -run-pass=regbankselect -regbankselect-fast -filetype=null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=amdgpu6.00 -run-pass=regbankselect -regbankselect-greedy -filetype=null %s 2>&1 | FileCheck %s # Check behavior for illegal copies. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir index cafc0ffed0f78..a8c134f213988 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s --- name: gep_p0_s_k diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll index 552bc2bf465d6..e5a3a8d7641cc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,GISEL %s -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,CGP %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir index 61aeb55b910fd..50c572026d384 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -run-pass=instruction-select -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -run-pass=instruction-select -o - %s | FileCheck %s # Checks MI Flags are preserved on selected instructions. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir index b0d3a1e482f14..eab41af7edf77 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=legalizer %s -o - | FileCheck %s --- name: test diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll index 27f58ff9f0438..b8261ef7d7f20 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,GISEL %s -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,CGP %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll index 16e452c0f3877..b6e0fdd5a7cc1 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,GISEL %s -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,CGP %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll index 029bcc06e6f85..cfe86e2b7081a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgpu6.00-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgpu6.00-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll index cd4605256d2d0..a25a78d3c0213 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,GISEL %s -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=CHECK,CGP %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgpu6.00-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll index 47544a4c11afb..69dca2f91764c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s -; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgpu6.00-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s +; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgpu6.00-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
