https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/209818
>From 4758a7f4a92327656055918233734a25233d561b Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 26 Jun 2026 16:53:18 +0200 Subject: [PATCH] AMDGPU: Migrate DebugInfo tests to new subarch triples (58) Mostly mechanical by script Co-authored-by: Claude (Opus 4.8) <[email protected]> --- llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll | 2 +- llvm/test/DebugInfo/AMDGPU/cfi.ll | 2 +- llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll | 4 ++-- llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll | 4 ++-- llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll | 2 +- llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll | 4 ++-- .../DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s | 2 +- llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll | 4 ++-- llvm/test/DebugInfo/AMDGPU/print-reg-name.s | 2 +- llvm/test/DebugInfo/AMDGPU/variable-locations.ll | 4 ++-- llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll | 2 +- 11 files changed, 16 insertions(+), 16 deletions(-) diff --git a/llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll b/llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll index c5f7602d1e7fc..0e5b1b7cca281 100644 --- a/llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll +++ b/llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s ; ; AMDGPUTargetLowering::performStoreCombine inserts a bitcast to convert ; <1 x float> to i32 for the store. That synthetic bitcast must carry the diff --git a/llvm/test/DebugInfo/AMDGPU/cfi.ll b/llvm/test/DebugInfo/AMDGPU/cfi.ll index c7c23bc632fe7..52eebe63008b2 100644 --- a/llvm/test/DebugInfo/AMDGPU/cfi.ll +++ b/llvm/test/DebugInfo/AMDGPU/cfi.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - %s | llvm-dwarfdump -debug-frame - | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -filetype=obj -o - %s | llvm-dwarfdump -debug-frame - | FileCheck %s ; CHECK: .debug_frame contents: ; CHECK: 00000000 0000000c ffffffff CIE diff --git a/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll b/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll index 53a814402a87d..fa5ee711b7619 100644 --- a/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll +++ b/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll @@ -1,8 +1,8 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu8.03--amdhsa -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; LLVM IR generated with the following command and OpenCL source: ; -; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> +; $clang -cl-std=CL2.0 -g -O0 -target amdgpu8.03-amd-amdhsa -S -emit-llvm <path-to-file> ; ; kernel void kernel1(global int addrspace(5)*A) { ; *A = 11; diff --git a/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll b/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll index 834702225a853..d71d70d59ba37 100644 --- a/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll +++ b/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll @@ -1,11 +1,11 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck %s ; Make sure we do not crash during scheduling when DBG_VALUE is the first ; instruction in the basic block. ; LLVM IR generated with the following command and OpenCL source: ; -; $clang -cl-std=CL2.0 -g -O2 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> +; $clang -cl-std=CL2.0 -g -O2 -target amdgpu8.03-amd-amdhsa -S -emit-llvm <path-to-file> ; ; kernel void kernel1(global int *A, global int *B) { ; if (*A == 1) { diff --git a/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll b/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll index 522f386a7c6cd..f81a57f12173b 100644 --- a/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll +++ b/llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s ; Verify that the debug locations in this function are correct, in particular ; that the location for %cast doesn't appear in the block of %lab. diff --git a/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll b/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll index 01fb4399af0aa..cc0a3430fe424 100644 --- a/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll +++ b/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll @@ -1,8 +1,8 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v - 2>&1 | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu8.03--amdhsa -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v - 2>&1 | FileCheck %s ; LLVM IR generated with the following command and OpenCL source: ; -; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> +; $clang -cl-std=CL2.0 -g -O0 -target amdgpu8.03-amd-amdhsa -S -emit-llvm <path-to-file> ; ; kernel void kernel1(global int addrspace(5)*A) { ; *A = 11; diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s index d742cfc49689c..2599f3abfa18a 100644 --- a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s +++ b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1100 -filetype=obj %s | llvm-dwarfdump -debug-frame - | FileCheck %s +; RUN: llvm-mc -triple=amdgpu11.00-amd-amdhsa -filetype=obj %s | llvm-dwarfdump -debug-frame - | FileCheck %s .text .cfi_sections .debug_frame diff --git a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll index f631c95e2d04b..a289d83951c7a 100644 --- a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll +++ b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll @@ -1,8 +1,8 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu8.03--amdhsa -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s ; LLVM IR generated with the following command and OpenCL source: ; -; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> +; $clang -cl-std=CL2.0 -g -O0 -target amdgpu8.03-amd-amdhsa -S -emit-llvm <path-to-file> ; ; kernel void kernel1() { ; global int addrspace(5)*FuncVar0 = 0; diff --git a/llvm/test/DebugInfo/AMDGPU/print-reg-name.s b/llvm/test/DebugInfo/AMDGPU/print-reg-name.s index fdd2c59bdd168..c296767192d33 100644 --- a/llvm/test/DebugInfo/AMDGPU/print-reg-name.s +++ b/llvm/test/DebugInfo/AMDGPU/print-reg-name.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm %s | FileCheck %s +; RUN: llvm-mc -triple=amdgpu9.00-amd-amdhsa -filetype=asm %s | FileCheck %s ; FIXME: Currently we can't print register names in CFI directives ; without extending MC to support DWARF register names that are distinct diff --git a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll index ce69180e01539..276a9299cb777 100644 --- a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll +++ b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll @@ -1,8 +1,8 @@ -; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s +; RUN: llc -O0 -mtriple=amdgpu8.03-amd-amdhsa -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s ; LLVM IR generated with the following command and OpenCL source: ; -; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> +; $clang -cl-std=CL2.0 -g -O0 -target amdgpu8.03-amd-amdhsa -S -emit-llvm <path-to-file> ; ; global int GlobA; ; global int GlobB; diff --git a/llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll b/llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll index 98ceb75f4912a..446244e6cf3d5 100644 --- a/llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll +++ b/llvm/test/DebugInfo/AMDGPU/wqm-wwm-debug-loc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu12.00--amdpal < %s | FileCheck %s ; Test that compiler-generated WQM/WWM exec mask manipulation instructions ; have debug locations attached. _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
