llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Petar Avramovic (petar-avramovic) <details> <summary>Changes</summary> For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark them with usesCustomInserter which will be used to add pre-RA register allocation hints to preferably assign dst and src2 to the same physical register. When the hint is satisfied, canMapVOP3PToVOPD recognises the instruction as eligible for VOPD pairing by checking if it is VOP2 like: dst==src2, no source modifiers, no clamp, and src1 is a register. Mark both instructions as commutable to allow a literal in src1 to be moved to src0, since VOPD only permits a literal in src0. Original patch had a bug where it did not check if physical src registers match register class of appropriate operand in fullVOPD instructions, check is now done via isValidVOPDSrc. --- Patch is 87.92 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196516.diff 7 Files Affected: - (modified) llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp (+34-1) - (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+8) - (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+6) - (modified) llvm/lib/Target/AMDGPU/VOP3PInstructions.td (+8-5) - (modified) llvm/lib/Target/AMDGPU/VOPInstructions.td (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll (+163-69) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll (+447-525) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp index 0e1d3693b487c..54d1910a7c05d 100644 --- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp +++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp @@ -56,6 +56,38 @@ bool isValidVOPDSrc(const SIInstrInfo &TII, int VOPDOpc, unsigned CompIdx, return TII.getRegClass(TII.get(VOPDOpc), OpIdx)->contains(PhysSrcReg); } +static const MachineOperand &getNamedOp(const MachineInstr &MI, + AMDGPU::OpName Name) { + return MI.getOperand(getNamedOperandIdx(MI.getOpcode(), Name)); +} + +// Check if MI is a VOP3P instruction with operands that satisfy the constraints +// for mapping it to a VOP2/VOPD opcode: no modifiers, no clamp, src1 and src2 +// are registers (src0 can be register or literal), and src2 is same as dst. +static bool canMapVOP3PToVOPD(const MachineInstr &MI) { + unsigned Opc = MI.getOpcode(); + if (Opc != AMDGPU::V_DOT2_F32_F16 && Opc != AMDGPU::V_DOT2_F32_BF16) + return false; + // src0 can be register or literal + if (getNamedOp(MI, AMDGPU::OpName::src0_modifiers).getImm() != + SISrcMods::OP_SEL_1) + return false; + if (getNamedOp(MI, AMDGPU::OpName::src1_modifiers).getImm() != + SISrcMods::OP_SEL_1) + return false; + if (!getNamedOp(MI, AMDGPU::OpName::src1).isReg()) + return false; + if (getNamedOp(MI, AMDGPU::OpName::src2_modifiers).getImm() != + SISrcMods::OP_SEL_1) + return false; + if (!getNamedOp(MI, AMDGPU::OpName::src2).isReg()) + return false; + if (getNamedOp(MI, AMDGPU::OpName::clamp).getImm() != 0) + return false; + return getNamedOp(MI, AMDGPU::OpName::vdst).getReg() == + getNamedOp(MI, AMDGPU::OpName::src2).getReg(); +} + bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII, const MachineInstr &MIX, const MachineInstr &MIY, bool IsVOPD3, @@ -67,7 +99,8 @@ bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII, if (IsVOPD3 && !ST.hasVOPD3()) return false; - if (!IsVOPD3 && (TII.isVOP3(MIX) || TII.isVOP3(MIY))) + if (!IsVOPD3 && ((TII.isVOP3(MIX) && !canMapVOP3PToVOPD(MIX)) || + (TII.isVOP3(MIY) && !canMapVOP3PToVOPD(MIY)))) return false; if (TII.isDPP(MIX) || TII.isDPP(MIY)) return false; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 8f406f2d8ef74..9ab55ea177c16 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -7351,6 +7351,14 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MI.getOperand(0).setReg(OriginalExec); return BB; } + case AMDGPU::V_DOT2_F32_F16: + case AMDGPU::V_DOT2_F32_BF16: { + // Hint RA to assign dst and src2 the same physical register. + // For targets without VOP2, but with VOPD, variant of the instruction this + // is one of the conditions to attempt converting VOP3P to VOPD. + MRI.setSimpleHint(MI.getOperand(0).getReg(), MI.getOperand(6).getReg()); + return BB; + } default: if (TII->isImage(MI) || TII->isMUBUF(MI)) { if (!MI.mayStore()) diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 71d95a23e30d3..99b408e0cc35c 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -928,6 +928,12 @@ ComponentProps::ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout) { NumVOPD3Mods = 2; if (IsVOP3) SrcOperandsNum = 3; + } else if (Opcode == AMDGPU::V_DOT2_F32_F16 || + Opcode == AMDGPU::V_DOT2_F32_BF16) { + // VOP3P opcodes that have VOPD but don't have VOP2 version. Using VOPD3 + // path in getIndexOfSrcInMCOperands to get correct src operand indexes, + // but generating VOPD, not VOPD3. + NumVOPD3Mods = SrcOperandsNum; } else if (isSISrcFPOperand(OpDesc, getNamedOperandIdx(Opcode, OpName::src0))) { // All FP VOPD instructions have Neg modifiers for all operands except diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index f99367d198f26..ab2538c2f9f00 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -87,11 +87,13 @@ multiclass VOP3PInst<string OpName, VOPProfile P, } multiclass VOP3PInstDotWithDual<string OpName, VOPProfile P, - SDPatternOperator node = null_frag> { + SDPatternOperator node = null_frag, + bits<6> VOPDOp, string VOPDName> { def NAME : VOP3P_Pseudo<OpName, P, getVOP3PModPat<P, node, 1 /*HasExplicitClamp*/, 1/*IsDOT*/, - VOP3PModsDOT, VOP3PModsF32>.ret>; + VOP3PModsDOT, VOP3PModsF32>.ret>, + VOPD_Component<VOPDOp, VOPDName>; let SubtargetPredicate = isGFX11Plus in { if P.HasExtVOP3DPP then def _dpp : VOP3_DPP_Pseudo<OpName, P> { @@ -692,12 +694,12 @@ defm V_DOT2_U32_U16 : VOP3PInst<"v_dot2_u32_u16", VOP3P_Profile<VOP_I32_V2I16_V2I16_I32>, int_amdgcn_udot2, 1>; } // End OtherPredicates = [HasDot2Insts] -let OtherPredicates = [HasDot10Insts] in +let OtherPredicates = [HasDot10Insts], isCommutable = 1, usesCustomInserter = 1 in defm V_DOT2_F32_F16 : VOP3PInstDotWithDual<"v_dot2_f32_f16", VOP3P_Profile<VOP_F32_V2F16_V2F16_F32, VOP3_REGULAR, /*HasDPP*/ 1>, - AMDGPUfdot2>; + AMDGPUfdot2, 0xC, "v_dot2acc_f32_f16">; let OtherPredicates = [HasDot7Insts] in { defm V_DOT4_U32_U8 : VOP3PInst<"v_dot4_u32_u8", @@ -721,9 +723,10 @@ def DOT2_BF16_Profile let SubtargetPredicate = HasDot12Insts in { +let isCommutable = 1, usesCustomInserter = 1 in defm V_DOT2_F32_BF16 : VOP3PInstDotWithDual<"v_dot2_f32_bf16", DOT2_BF16_Profile, - int_amdgcn_fdot2_f32_bf16>; + int_amdgcn_fdot2_f32_bf16, 0xD, "v_dot2acc_f32_bf16">; } // End SubtargetPredicate = HasDot12Insts diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index c2543e75dea6a..a379785616c6c 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -34,8 +34,8 @@ class VOP <string opName> { string OpName = opName; } -// First 13 insts from VOPDY are also VOPDX. DOT2ACC_F32_BF16 is omitted -defvar VOPDX_Max_Index = 12; +// First 13 insts from VOPDY are also VOPDX. +defvar VOPDX_Max_Index = 13; defvar VOPD3X_Max_Index = 36; class VOPD_Component<bits<6> OpIn, string vOPDName> { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll index 8751f3176f856..d1bf194ec93cf 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll @@ -225,7 +225,7 @@ define float @v_fdot2_f32_bf16_inline_literal_b(<2 x bfloat> %a, float %c) { ; ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_inline_literal_b: ; GFX11PLUS: ; %bb.0: -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, 0x40004000, v1 +; GFX11PLUS: v_dot2_f32_bf16 v0, 0x40004000, v0, v1 %ret = tail call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> <bfloat 2.0, bfloat 2.0>, float %c, i1 false) ret float %ret } @@ -373,7 +373,7 @@ define float @v_fdot2_f32_bf16_inline_literal_b_clamp(<2 x bfloat> %a, float %c) ; ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_inline_literal_b_clamp: ; GFX11PLUS: ; %bb.0: -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, 0x40004000, v1 clamp +; GFX11PLUS: v_dot2_f32_bf16 v0, 0x40004000, v0, v1 clamp %ret = tail call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> <bfloat 2.0, bfloat 2.0>, float %c, i1 true) ret float %ret } @@ -395,9 +395,116 @@ define float @v_fdot2_f32_bf16_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c, ; ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual: ; GFX11PLUS: ; %bb.0: -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dual_dot2acc_f32_bf16 v2, v0, v1 :: v_dual_dot2acc_f32_bf16 v5, v3, v4 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 + %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false) + %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) + %r = fadd float %r0, %r1 + ret float %r +} + +define float @v_fdot2_f32_bf16_dual_sgpr_src0_x(<2 x bfloat> inreg %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) { +; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_x: +; GFX950: ; %bb.0: +; GFX950: v_dot2c_f32_bf16_e32 v1, s0, v0 +; GFX950: v_dot2c_f32_bf16_e32 v4, v2, v3 +; GFX950: v_add_f32_e32 v0, v1, v4 +; +; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_x: +; GFX11PLUS: ; %bb.0: +; GFX11PLUS: v_dual_dot2acc_f32_bf16 v1, s0, v0 :: v_dual_dot2acc_f32_bf16 v4, v2, v3 +; GFX11PLUS: v_add_f32_e32 v0, v1, v4 + %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false) + %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) + %r = fadd float %r0, %r1 + ret float %r +} + +define float @v_fdot2_f32_bf16_dual_sgpr_src1_x(<2 x bfloat> %a, <2 x bfloat> inreg %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) { +; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_x: +; GFX950: ; %bb.0: +; GFX950: v_dot2c_f32_bf16_e32 v1, s0, v0 +; GFX950: v_dot2c_f32_bf16_e32 v4, v2, v3 +; GFX950: v_add_f32_e32 v0, v1, v4 +; +; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_x: +; GFX11PLUS: ; %bb.0: +; GFX11PLUS: v_dot2_f32_bf16 v1, v0, s0, v1 +; GFX11PLUS: v_dot2_f32_bf16 v4, v2, v3, v4 +; GFX11PLUS: v_add_f32_e32 v0, v1, v4 + %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false) + %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) + %r = fadd float %r0, %r1 + ret float %r +} + +define float @v_fdot2_f32_bf16_dual_sgpr_src2_x(<2 x bfloat> %a, <2 x bfloat> %b, float inreg %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) { +; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_x: +; GFX950: ; %bb.0: +; GFX950: v_mov_b32_e32 v5, s0 +; GFX950: v_dot2c_f32_bf16_e32 v5, v0, v1 +; GFX950: v_dot2c_f32_bf16_e32 v4, v2, v3 +; GFX950: v_add_f32_e32 v0, v5, v4 +; +; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_x: +; GFX11PLUS: ; %bb.0: +; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, s0 +; GFX11PLUS: v_dot2_f32_bf16 v4, v2, v3, v4 +; GFX11PLUS: v_add_f32_e32 v0, v0, v4 + %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false) + %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) + %r = fadd float %r0, %r1 + ret float %r +} + +define float @v_fdot2_f32_bf16_dual_sgpr_src0_y(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> inreg %d, <2 x bfloat> %e, <2 x bfloat> %vopd_dst_pad, float %f) { +; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_y: +; GFX950: ; %bb.0: +; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1 +; GFX950: v_dot2c_f32_bf16_e32 v5, s0, v3 +; GFX950: v_add_f32_e32 v0, v2, v5 +; +; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src0_y: +; GFX11PLUS: ; %bb.0: +; GFX11PLUS: v_dual_dot2acc_f32_bf16 v2, v0, v1 :: v_dual_dot2acc_f32_bf16 v5, s0, v3 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 + %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false) + %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) + %r = fadd float %r0, %r1 + ret float %r +} + +define float @v_fdot2_f32_bf16_dual_sgpr_src1_y(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %vopd_dst_pad, <2 x bfloat> inreg %e, float %f) { +; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_y: +; GFX950: ; %bb.0: +; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1 +; GFX950: v_dot2c_f32_bf16_e32 v5, s0, v3 +; GFX950: v_add_f32_e32 v0, v2, v5 +; +; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src1_y: +; GFX11PLUS: ; %bb.0: +; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2 +; GFX11PLUS: v_dot2_f32_bf16 v5, v3, s0, v5 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 + %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false) + %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) + %r = fadd float %r0, %r1 + ret float %r +} + +define float @v_fdot2_f32_bf16_dual_sgpr_src2_y(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float inreg %f) { +; GFX950-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_y: +; GFX950: ; %bb.0: +; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1 +; GFX950: v_mov_b32_e32 v0, s0 +; GFX950: v_dot2c_f32_bf16_e32 v0, v3, v4 +; GFX950: v_add_f32_e32 v0, v2, v0 +; +; GFX11PLUS-LABEL: v_fdot2_f32_bf16_dual_sgpr_src2_y: +; GFX11PLUS: ; %bb.0: +; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2 +; GFX11PLUS: v_dot2_f32_bf16 v0, v3, v4, s0 +; GFX11PLUS: v_add_f32_e32 v0, v2, v0 %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false) %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) %r = fadd float %r0, %r1 @@ -407,15 +514,15 @@ define float @v_fdot2_f32_bf16_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c, define float @v_fdot2_f32_bf16_neg_a_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) { ; GFX950-LABEL: v_fdot2_f32_bf16_neg_a_dual: ; GFX950: ; %bb.0: -; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0] +; GFX950: v_dot2_f32_bf16 v2, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0] ; GFX950: v_dot2c_f32_bf16_e32 v5, v3, v4 -; GFX950: v_add_f32_e32 v0, v0, v5 +; GFX950: v_add_f32_e32 v0, v2, v5 ; ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_a_dual: ; GFX11PLUS: ; %bb.0: -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0] -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0] +; GFX11PLUS: v_dot2_f32_bf16 v5, v3, v4, v5 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 %neg.a = fneg <2 x bfloat> %a %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %neg.a, <2 x bfloat> %b, float %c, i1 false) %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) @@ -436,9 +543,8 @@ define float @v_fdot2_f32_bf16_neg_a_lo_dual(<2 x bfloat> %a, <2 x bfloat> %b, f ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_a_lo_dual: ; GFX11PLUS: ; %bb.0: ; GFX11PLUS: v_xor_b16 v0.l, 0x8000, v0.l -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 %a_lo = extractelement <2 x bfloat> %a, i32 0 %neg.a_lo = fneg bfloat %a_lo %neg_lo.a = insertelement <2 x bfloat> %a, bfloat %neg.a_lo, i32 0 @@ -462,9 +568,8 @@ define float @v_fdot2_f32_bf16_neg_a_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_a_hi_dual: ; GFX11PLUS: ; %bb.0: ; GFX11PLUS: v_xor_b16 v0.h, 0x8000, v0.h -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 %a_hi = extractelement <2 x bfloat> %a, i32 1 %neg.a_hi = fneg bfloat %a_hi %neg_hi.a = insertelement <2 x bfloat> %a, bfloat %neg.a_hi, i32 1 @@ -477,15 +582,15 @@ define float @v_fdot2_f32_bf16_neg_a_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f define float @v_fdot2_f32_bf16_neg_b_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) { ; GFX950-LABEL: v_fdot2_f32_bf16_neg_b_dual: ; GFX950: ; %bb.0: -; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0] +; GFX950: v_dot2_f32_bf16 v2, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0] ; GFX950: v_dot2c_f32_bf16_e32 v5, v3, v4 -; GFX950: v_add_f32_e32 v0, v0, v5 +; GFX950: v_add_f32_e32 v0, v2, v5 ; ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_b_dual: ; GFX11PLUS: ; %bb.0: -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0] -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0] +; GFX11PLUS: v_dot2_f32_bf16 v5, v3, v4, v5 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 %neg.b = fneg <2 x bfloat> %b %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %neg.b, float %c, i1 false) %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) @@ -506,9 +611,8 @@ define float @v_fdot2_f32_bf16_neg_b_lo_dual(<2 x bfloat> %a, <2 x bfloat> %b, f ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_b_lo_dual: ; GFX11PLUS: ; %bb.0: ; GFX11PLUS: v_xor_b16 v1.l, 0x8000, v1.l -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 %b_lo = extractelement <2 x bfloat> %b, i32 0 %neg.b_lo = fneg bfloat %b_lo %neg_lo.b = insertelement <2 x bfloat> %b, bfloat %neg.b_lo, i32 0 @@ -532,9 +636,8 @@ define float @v_fdot2_f32_bf16_neg_b_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_b_hi_dual: ; GFX11PLUS: ; %bb.0: ; GFX11PLUS: v_xor_b16 v1.h, 0x8000, v1.h -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 %b_hi = extractelement <2 x bfloat> %b, i32 1 %neg.b_hi = fneg bfloat %b_hi %neg_hi.b = insertelement <2 x bfloat> %b, bfloat %neg.b_hi, i32 1 @@ -547,15 +650,15 @@ define float @v_fdot2_f32_bf16_neg_b_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f define float @v_fdot2_f32_bf16_neg_c_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) { ; GFX950-LABEL: v_fdot2_f32_bf16_neg_c_dual: ; GFX950: ; %bb.0: -; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,0,1] +; GFX950: v_dot2_f32_bf16 v2, v0, v1, v2 neg_lo:[0,0,1] ; GFX950: v_dot2c_f32_bf16_e32 v5, v3, v4 -; GFX950: v_add_f32_e32 v0, v0, v5 +; GFX950: v_add_f32_e32 v0, v2, v5 ; ; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_c_dual: ; GFX11PLUS: ; %bb.0: -; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,0,1] -; GFX11PLUS: v_dot2_f32_bf16 v1, v3, v4, v5 -; GFX11PLUS: v_add_f32_e32 v0, v0, v1 +; GFX11PLUS: v_dot2_f32_bf16 v2, v0, v1, v2 neg_lo:[0,0,1] +; GFX11PLUS: v_dot2_f32_bf16 v5, v3, v4, v5 +; GFX11PLUS: v_add_f32_e32 v0, v2, v5 %neg.c = fneg float %c %r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %neg.c, i1 false) %r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false) @@ -566,15 +669,15 @@ define float @v_fdot2_f32_bf16_neg_c_dual(<2 x bfloat> %a, <2 x bfloat> %b, floa define float @v_fdot2_f32_bf16_abs_c_dual(<2 x bfloat> %a, <2 x bfloat> %b, float %c, <2 x bfloat> %d, <2 x bfloat> %e, float %f) { ; GFX950-LABEL: v_fdot2_f32_bf16_abs_c_dual: ; GFX950: ; %bb.0: -; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 neg_hi:[0,0,1] +; GFX950: v_dot2_f32_bf16 v2, v0, v1, v2 neg_hi:[0,0,1] ; GFX950: v_do... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/196516 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
