llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Petar Avramovic (petar-avramovic) <details> <summary>Changes</summary> Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively. The actual error was the artifact combiner creating a copy between f32/i32 which fails in the machine verifier. Maybe we could create a bitcast there. However i32 is more efficient for us and matches well with how argument lowering keeps f16 and bf16 in i32 copies to/from physical registers. Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16), and doing widen scalar to 32 bit type, i32 makes more sense since store will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16) compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if we assume input was really in f32 format. --- Patch is 1.36 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210095.diff 21 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll (-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll (-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll (+3-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+2-3) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir (+486-486) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir (+557-557) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir (+2011-2011) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir (+1164-1164) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir (+963-963) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-store-s16-true16.mir (+28-28) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (+108-108) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir (+24-24) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll (-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll (-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-return-types.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/freeze.ll (+6-6) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 73dbd32b88d4b..89b03c7210105 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -1772,7 +1772,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, // May need relegalization for the scalars. return std::pair(0, EltTy); }) - .minScalar(0, S32) + .widenScalarIf(scalarNarrowerThan(0, 32), changeTo(0, LLT::integer(32))) .narrowScalarIf(isTruncStoreToSizePowerOf2(0), getScalarTypeFromMemDesc(0)) .widenScalarToNextPow2(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir index b3cbb2a86d31c..237abb08ce0f8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir @@ -180,7 +180,7 @@ body: | ; CHECK: liveins: $vgpr0_vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 - ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1) ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll index 712785a1b237b..fe64a5b1bbcdc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; UNSUPPORTED: true ; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX7 %s ; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll index e4d06bcc2cb1b..f555a2073b46c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; UNSUPPORTED: true ; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX6 %s ; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX7 %s ; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX8 %s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll index 5e41d2388f828..717c848d36f7c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll @@ -1,8 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; UNSUPPORTED: true -; xUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX8 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; TODO: Merge with atomic_load_local.ll diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll index b0f5431bd5452..e850c36b98d30 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; UNSUPPORTED: true -; RUN: llc -global-isel -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgpu7.04 < %s | FileCheck --check-prefix=CI %s -; RUN: llc -global-isel -global-isel-abort=2 -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgpu8.02 < %s | FileCheck --check-prefix=VI %s +; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgpu7.04 < %s | FileCheck --check-prefix=CI %s +; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgpu8.02 < %s | FileCheck --check-prefix=VI %s define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { ; CI-LABEL: frem_f16: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir index 95b9c4bb3198a..07ed98b150274 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir @@ -16,7 +16,7 @@ body: | ; CI: liveins: $vgpr0_vgpr1 ; CI-NEXT: {{ $}} ; CI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 - ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) + ; CI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; CI-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -25,7 +25,7 @@ body: | ; VI: liveins: $vgpr0_vgpr1 ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 - ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) + ; VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; VI-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -34,7 +34,7 @@ body: | ; GFX9: liveins: $vgpr0_vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) + ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; GFX9-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -43,7 +43,7 @@ body: | ; GFX11: liveins: $vgpr0_vgpr1 ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 - ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) + ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4) ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; GFX11-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -63,7 +63,7 @@ body: | ; CI: liveins: $vgpr0_vgpr1 ; CI-NEXT: {{ $}} ; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; CI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) ; CI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; CI-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -72,7 +72,7 @@ body: | ; VI: liveins: $vgpr0_vgpr1 ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; VI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; VI-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -81,7 +81,7 @@ body: | ; GFX9: liveins: $vgpr0_vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; GFX9-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; GFX9-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -90,7 +90,7 @@ body: | ; GFX11: liveins: $vgpr0_vgpr1 ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; GFX11-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; GFX11-NEXT: $vgpr0 = COPY [[AND]](s32) @@ -110,29 +110,29 @@ body: | ; CI: liveins: $vgpr0_vgpr1 ; CI-NEXT: {{ $}} ; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) - ; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; CI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) + ; CI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; VI-LABEL: name: test_load_constant_s8_align4 ; VI: liveins: $vgpr0_vgpr1 ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) - ; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) + ; VI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX9-LABEL: name: test_load_constant_s8_align4 ; GFX9: liveins: $vgpr0_vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) - ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) + ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX11-LABEL: name: test_load_constant_s8_align4 ; GFX11: liveins: $vgpr0_vgpr1 ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) - ; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4) + ; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](i32) %0:_(p4) = COPY $vgpr0_vgpr1 %1:_(s8) = G_LOAD %0 :: (load (s8), align 4, addrspace 4) %2:_(s32) = G_ANYEXT %1 @@ -149,29 +149,29 @@ body: | ; CI: liveins: $vgpr0_vgpr1 ; CI-NEXT: {{ $}} ; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) - ; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; CI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; CI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; VI-LABEL: name: test_load_constant_s8_align1 ; VI: liveins: $vgpr0_vgpr1 ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) - ; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; VI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX9-LABEL: name: test_load_constant_s8_align1 ; GFX9: liveins: $vgpr0_vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) - ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX11-LABEL: name: test_load_constant_s8_align1 ; GFX11: liveins: $vgpr0_vgpr1 ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) - ; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX11-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; GFX11-NEXT: $vgpr0 = COPY [[LOAD]](i32) %0:_(p4) = COPY $vgpr0_vgpr1 %1:_(s8) = G_LOAD %0 :: (load (s8), align 1, addrspace 4) %2:_(s32) = G_ANYEXT %1 @@ -188,22 +188,22 @@ body: | ; CI: liveins: $vgpr0_vgpr1 ; CI-NEXT: {{ $}} ; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) - ; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; CI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) + ; CI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; VI-LABEL: name: test_load_constant_s16_align4 ; VI: liveins: $vgpr0_vgpr1 ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) - ; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) + ; VI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX9-LABEL: name: test_load_constant_s16_align4 ; GFX9: liveins: $vgpr0_vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) - ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) + ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX11-TRUE16-LABEL: name: test_load_constant_s16_align4 ; GFX11-TRUE16: liveins: $vgpr0_vgpr1 @@ -217,8 +217,8 @@ body: | ; GFX11-FAKE16: liveins: $vgpr0_vgpr1 ; GFX11-FAKE16-NEXT: {{ $}} ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX11-FAKE16-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) - ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX11-FAKE16-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4) + ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[LOAD]](i32) %0:_(p4) = COPY $vgpr0_vgpr1 %1:_(s16) = G_LOAD %0 :: (load (s16), align 4, addrspace 4) %2:_(s32) = G_ANYEXT %1 @@ -235,22 +235,22 @@ body: | ; CI: liveins: $vgpr0_vgpr1 ; CI-NEXT: {{ $}} ; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) - ; CI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; CI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) + ; CI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; VI-LABEL: name: test_load_constant_s16_align2 ; VI: liveins: $vgpr0_vgpr1 ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) - ; VI-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) + ; VI-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX9-LABEL: name: test_load_constant_s16_align2 ; GFX9: liveins: $vgpr0_vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) - ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX9-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) + ; GFX9-NEXT: $vgpr0 = COPY [[LOAD]](i32) ; ; GFX11-TRUE16-LABEL: name: test_load_constant_s16_align2 ; GFX11-TRUE16: liveins: $vgpr0_vgpr1 @@ -264,8 +264,8 @@ body: | ; GFX11-FAKE16: liveins: $vgpr0_vgpr1 ; GFX11-FAKE16-NEXT: {{ $}} ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; GFX11-FAKE16-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) - ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[LOAD]](s32) + ; GFX11-FAKE16-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4) + ; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[LOAD]](i32) %0:_(p4) = COPY $vgpr0_vgpr1 %1:_(s16) = G_LOAD %0 :: (load (s16), align 2, addrspace 4) %2:_(s32) = G_ANYEXT %1 @@ -282,53 +282,53 @@ body: | ; CI: liveins: $vgpr0_vgpr1 ; CI-NEXT: {{ $}} ; CI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p4) :: (load (s8), addrspace 4) - ; CI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) - ; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s8) from unknown-address + 1, addrspace 4) - ; CI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) - ; CI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] - ; CI-NEXT: $vgpr0 = COPY [[OR]](s32) + ; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; CI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1 + ; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64) + ; CI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (load (s8) from unknown-address + 1, addrspace 4) + ; CI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 8 + ; CI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[LOAD]], [[C1]](i32) + ; CI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[ZEXTLOAD]] + ; CI-NEXT: $vgpr0 = COPY [[OR]](i32) ; ; VI-LABEL: name: test_load_constant_s16_align1 ; VI: liveins: $vgpr0_vgpr1 ; VI-NEXT: {{ $}} ; VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 - ; VI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p4) :: (load (s8), addrspace 4) - ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64) - ; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s8) from unknown-address + 1, addrspace 4) - ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; VI-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) - ; VI-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] - ; VI-NEXT: $vgpr0 = COPY [[OR]](s32) + ; VI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[COPY]](p4) :: (load (s8), addrspace 4) + ; VI-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1 + ; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64) + ; VI-NEXT: [[LOAD:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD]](p4) :: (load (s8) from unknown-address + 1, addrspace 4) + ; VI-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 8 + ; VI-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[LOAD]], [[C1]](i32) + ; VI-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[SHL]], [[ZEXTLOAD]] + ; VI-NEXT: $vgpr0 = COPY [[OR]](i32) ; ; GFX9-LABEL: name: test_load_constant_s16_align1 ; GFX9: liveins: $vgpr0_vgpr1 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: [[COPY:%... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/210095 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
