llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-globalisel Author: Petar Avramovic (petar-avramovic) <details> <summary>Changes</summary> We could get away with just the type from MMO in most cases, but MMO splitting creates MMO with LLT::scalar and we prefer integer. --- Patch is 1.02 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210096.diff 14 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll (+164-19) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir (+1077-957) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir (+828-738) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir (+1622-1442) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir (+842-722) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir (+250-220) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (+121-121) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir (+13-13) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-weird-size.ll (+6-6) - (modified) llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll (+38-26) - (modified) llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll (+38-26) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 89b03c7210105..c2efcd626a9c1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -144,7 +144,7 @@ static LegalizeMutation moreEltsToNext32Bit(unsigned TypeIdx) { static LegalizeMutation getScalarTypeFromMemDesc(unsigned TypeIdx) { return [=](const LegalityQuery &Query) { unsigned MemSize = Query.MMODescrs[0].MemoryTy.getSizeInBits(); - return std::make_pair(TypeIdx, LLT::scalar(MemSize)); + return std::make_pair(TypeIdx, LLT::integer(MemSize)); }; } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll index f13eac5623c40..fbdaee61479bf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll @@ -4,11 +4,11 @@ ; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX942 %s ; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+real-true16,-promote-alloca < %s | FileCheck -check-prefix=GFX12 %s -; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX9 %s -; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX10 %s -; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX942 %s -; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX11 %s -; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -global-isel -global-isel-abort=2 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+real-true16,-unaligned-access-mode,-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX12 %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX9 %s +; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca,+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX10 %s +; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX942 %s +; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=-unaligned-access-mode,-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX11 %s +; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -global-isel -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds -mattr=+real-true16,-unaligned-access-mode,-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX12 %s define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) { ; GFX9-LABEL: store_load_sindex_kernel: @@ -2570,10 +2570,39 @@ define void @store_load_i64_unaligned(ptr addrspace(5) nocapture %arg) { ; UNALIGNED_GFX9: ; %bb.0: ; %bb ; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; UNALIGNED_GFX9-NEXT: v_mov_b32_e32 v1, 15 -; UNALIGNED_GFX9-NEXT: v_mov_b32_e32 v2, 0 -; UNALIGNED_GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off ; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) -; UNALIGNED_GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc +; UNALIGNED_GFX9-NEXT: v_mov_b32_e32 v1, 0 +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off offset:1 +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off offset:2 +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off offset:3 +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off offset:4 +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off offset:5 +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off offset:6 +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_store_byte v0, v1, off offset:7 +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off glc +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: ; kill: killed $vgpr0 +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off offset:1 glc +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off offset:2 glc +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off offset:3 glc +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off offset:4 glc +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off offset:5 glc +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off offset:6 glc +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: scratch_load_ubyte v1, v0, off offset:7 glc ; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) ; UNALIGNED_GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -2582,29 +2611,116 @@ define void @store_load_i64_unaligned(ptr addrspace(5) nocapture %arg) { ; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; UNALIGNED_GFX10-NEXT: v_mov_b32_e32 v1, 15 ; UNALIGNED_GFX10-NEXT: v_mov_b32_e32 v2, 0 -; UNALIGNED_GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v1, off ; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; UNALIGNED_GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v2, off offset:1 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v2, off offset:2 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v2, off offset:3 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v2, off offset:4 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v2, off offset:5 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v2, off offset:6 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: scratch_store_byte v0, v2, off offset:7 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v1, v0, off glc dlc +; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v1, v0, off offset:1 glc dlc +; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v1, v0, off offset:2 glc dlc +; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v1, v0, off offset:3 glc dlc +; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v1, v0, off offset:4 glc dlc +; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v1, v0, off offset:5 glc dlc +; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v1, v0, off offset:6 glc dlc +; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX10-NEXT: scratch_load_ubyte v0, v0, off offset:7 glc dlc ; UNALIGNED_GFX10-NEXT: s_waitcnt vmcnt(0) ; UNALIGNED_GFX10-NEXT: s_setpc_b64 s[30:31] ; ; UNALIGNED_GFX942-LABEL: store_load_i64_unaligned: ; UNALIGNED_GFX942: ; %bb.0: ; %bb ; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; UNALIGNED_GFX942-NEXT: v_mov_b64_e32 v[2:3], 15 -; UNALIGNED_GFX942-NEXT: scratch_store_dwordx2 v0, v[2:3], off sc0 sc1 +; UNALIGNED_GFX942-NEXT: v_mov_b32_e32 v1, 15 +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off sc0 sc1 ; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) -; UNALIGNED_GFX942-NEXT: scratch_load_dwordx2 v[0:1], v0, off sc0 sc1 +; UNALIGNED_GFX942-NEXT: v_mov_b32_e32 v1, 0 +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off offset:3 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off offset:5 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off offset:6 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_store_byte v0, v1, off offset:7 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: ; kill: killed $vgpr0 +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off offset:1 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off offset:2 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off offset:3 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off offset:4 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off offset:5 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off offset:6 sc0 sc1 +; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX942-NEXT: scratch_load_ubyte v1, v0, off offset:7 sc0 sc1 ; UNALIGNED_GFX942-NEXT: s_waitcnt vmcnt(0) ; UNALIGNED_GFX942-NEXT: s_setpc_b64 s[30:31] ; ; UNALIGNED_GFX11-LABEL: store_load_i64_unaligned: ; UNALIGNED_GFX11: ; %bb.0: ; %bb ; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; UNALIGNED_GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_mov_b32 v2, 0 -; UNALIGNED_GFX11-NEXT: scratch_store_b64 v0, v[1:2], off dlc +; UNALIGNED_GFX11-NEXT: v_mov_b16_e32 v1.l, 15 +; UNALIGNED_GFX11-NEXT: v_mov_b16_e32 v1.h, 0 +; UNALIGNED_GFX11-NEXT: scratch_store_b8 v0, v1, off dlc ; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; UNALIGNED_GFX11-NEXT: scratch_load_b64 v[0:1], v0, off glc dlc +; UNALIGNED_GFX11-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:1 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:2 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:3 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:4 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:5 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:6 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:7 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v1, v0, off glc dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v1, v0, off offset:1 glc dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v1, v0, off offset:2 glc dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v1, v0, off offset:3 glc dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v1, v0, off offset:4 glc dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v1, v0, off offset:5 glc dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v1, v0, off offset:6 glc dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX11-NEXT: scratch_load_u8 v0, v0, off offset:7 glc dlc ; UNALIGNED_GFX11-NEXT: s_waitcnt vmcnt(0) ; UNALIGNED_GFX11-NEXT: s_setpc_b64 s[30:31] ; @@ -2615,11 +2731,40 @@ define void @store_load_i64_unaligned(ptr addrspace(5) nocapture %arg) { ; UNALIGNED_GFX12-NEXT: s_wait_samplecnt 0x0 ; UNALIGNED_GFX12-NEXT: s_wait_bvhcnt 0x0 ; UNALIGNED_GFX12-NEXT: s_wait_kmcnt 0x0 -; UNALIGNED_GFX12-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_mov_b32 v2, 0 +; UNALIGNED_GFX12-NEXT: v_mov_b16_e32 v1.l, 15 +; UNALIGNED_GFX12-NEXT: v_mov_b16_e32 v1.h, 0 ; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 -; UNALIGNED_GFX12-NEXT: scratch_store_b64 v0, v[1:2], off scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: scratch_store_b8 v0, v1, off scope:SCOPE_SYS ; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 -; UNALIGNED_GFX12-NEXT: scratch_load_b64 v[0:1], v0, off scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:1 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:2 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:3 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:4 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:5 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:6 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_store_d16_hi_b8 v0, v1, off offset:7 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v1, v0, off scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v1, v0, off offset:1 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v1, v0, off offset:2 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v1, v0, off offset:3 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v1, v0, off offset:4 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v1, v0, off offset:5 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v1, v0, off offset:6 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 +; UNALIGNED_GFX12-NEXT: scratch_load_u8 v0, v0, off offset:7 scope:SCOPE_SYS ; UNALIGNED_GFX12-NEXT: s_wait_loadcnt 0x0 ; UNALIGNED_GFX12-NEXT: s_setpc_b64 s[30:31] bb: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir index 07ed98b150274..0fc41105a1a72 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir @@ -908,14 +908,16 @@ body: | ; CI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[OR]](s32) ; CI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) - ; CI-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4) - ; CI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) - ; CI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4) - ; CI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD1]], [[C1]](s32) - ; CI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]] - ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR1]](s32) - ; CI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 - ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32) + ; CI-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4) + ; CI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 2 + ; CI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C3]](i64) + ; CI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4) + ; CI-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; CI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[LOAD1]], [[C4]](i32) + ; CI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[SHL1]], [[ZEXTLOAD1]] + ; CI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR1]](i32) + ; CI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C5]](s32) ; CI-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[ZEXT]] ; CI-NEXT: $vgpr0_vgpr1 = COPY [[OR2]](s64) ; @@ -933,14 +935,16 @@ body: | ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[OR]](s32) ; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64) - ; VI-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4) - ; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C]](s64) - ; VI-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4) - ; VI-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD1]], [[C1]](s32) - ; VI-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[ZEXTLOAD1]] - ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR1]](s32) - ; VI-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 - ; VI-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s32) + ; VI-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(i32) = G_ZEXTLOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4) + ; VI-NEXT: [[C3:%[0-9]+]]:_(i64) = G_CONSTANT i64 2 + ; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[PTR_ADD1]], [[C3]](i64) + ; VI-NEXT: [[LOAD1:%[0-9]+]]:_(i32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4) + ; VI-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; VI-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[LOAD1]], [[C4]](i32) + ; VI-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[SHL1]], [[ZEXTLOAD1]] + ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR1]](i32) + ; VI-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; VI-NEXT: [[SHL2:%[0-... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/210096 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
