llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Petar Avramovic (petar-avramovic) <details> <summary>Changes</summary> Here we also had to change comparisons to extended LLTs to avoid matching bfloats. In the old scalar version, before the switch to extended LLTs, s16 was treated as f16 and bf16 was combined as if it were f16. --- Patch is 896.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210102.diff 10 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp (+11-9) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll (+912-86) - (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll (+71-15) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll (+290-131) - (modified) llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll (+241-114) - (modified) llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll (+536-218) - (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+3710-1700) - (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+3710-1700) - (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+2772-1263) - (modified) llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll (+141-71) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp index a75c093a9e7ff..a325170e89e9b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp @@ -431,7 +431,7 @@ static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI, const MachineInstr *Def = MRI.getVRegDef(Reg); if (Def->getOpcode() == TargetOpcode::G_FPEXT) { Register SrcReg = Def->getOperand(1).getReg(); - return MRI.getType(SrcReg) == LLT::scalar(16); + return MRI.getType(SrcReg) == LLT::float16(); } if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) { @@ -450,7 +450,9 @@ bool AMDGPUCombinerHelper::matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src2) const { assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC); Register SrcReg = MI.getOperand(1).getReg(); - if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::scalar(32)) + if (MRI.getType(MI.getOperand(0).getReg()) != LLT::float16()) + return false; + if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::float32()) return false; return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) && @@ -463,9 +465,9 @@ void AMDGPUCombinerHelper::applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src2) const { // We expect fptrunc (fpext x) to fold out, and to constant fold any constant // sources. - Src0 = Builder.buildFPTrunc(LLT::scalar(16), Src0).getReg(0); - Src1 = Builder.buildFPTrunc(LLT::scalar(16), Src1).getReg(0); - Src2 = Builder.buildFPTrunc(LLT::scalar(16), Src2).getReg(0); + Src0 = Builder.buildFPTrunc(LLT::float16(), Src0).getReg(0); + Src1 = Builder.buildFPTrunc(LLT::float16(), Src1).getReg(0); + Src2 = Builder.buildFPTrunc(LLT::float16(), Src2).getReg(0); LLT Ty = MRI.getType(Src0); auto A1 = Builder.buildFMinNumIEEE(Ty, Src0, Src1); @@ -487,8 +489,8 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp( LLT ScalarDestTy = DestTy.getScalarType(); // TODO: Expected float type in ScalarDestTy - if ((ScalarDestTy != LLT::scalar(64) && ScalarDestTy != LLT::scalar(32) && - ScalarDestTy != LLT::scalar(16)) || + if ((ScalarDestTy != LLT::float64() && ScalarDestTy != LLT::float32() && + ScalarDestTy != LLT::float16()) || !MRI.hasOneNonDBGUse(Sel.getOperand(0).getReg())) return false; @@ -510,7 +512,7 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp( // For f32, only non-inline constants should be transformed. // TODO: Expected float32 - if (ScalarDestTy == LLT::scalar(32) && TII.isInlineConstant(*SelectTrueVal) && + if (ScalarDestTy == LLT::float32() && TII.isInlineConstant(*SelectTrueVal) && TII.isInlineConstant(*SelectFalseVal)) return false; @@ -522,7 +524,7 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp( return false; MatchInfo = [=, &MI](MachineIRBuilder &Builder) { - LLT IntDestTy = DestTy.changeElementType(LLT::scalar(32)); + LLT IntDestTy = DestTy.changeElementType(LLT::integer(32)); auto NewSel = Builder.buildSelect( IntDestTy, SelectCondReg, Builder.buildConstant(IntDestTy, SelectTrueLog2Val), diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll index fc7c4a57fe32e..0e5b3b25c51b0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll @@ -1,52 +1,126 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GFX6 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -global-isel -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GFX6 %s +; RUN: llc -global-isel -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s +; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s define float @v_pow_f32(float %x, float %y) { ; GFX6-LABEL: v_pow_f32: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 -; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 -; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX9-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 -; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_f32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo ; GFX10-NEXT: v_log_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo +; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo +; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 +; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %pow = call float @llvm.pow.f32(float %x, float %y) ret float %pow @@ -56,57 +130,190 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { ; GFX6-LABEL: v_pow_v2f32: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v4, 0x800000 +; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4 +; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4 +; GFX6-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v5 +; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4 ; GFX6-NEXT: v_log_f32_e32 v0, v0 +; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v4 ; GFX6-NEXT: v_log_f32_e32 v1, v1 -; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 -; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 +; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v6 +; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5] +; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 +; GFX6-NEXT: v_sub_f32_e32 v1, v1, v5 +; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000 +; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 +; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc +; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2 +; GFX6-NEXT: v_add_f32_e32 v0, v0, v7 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5] ; GFX6-NEXT: v_exp_f32_e32 v0, v0 +; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_exp_f32_e32 v1, v1 +; GFX6-NEXT: v_not_b32_e32 v4, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5] +; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_v2f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v4, 0x800000 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4 +; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4 +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; GFX8-NEXT: v_ldexp_f32 v0, v0, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4 ; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_ldexp_f32 v1, v1, v4 ; GFX8-NEXT: v_log_f32_e32 v1, v1 -; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 -; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 +; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v6 +; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5] +; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 +; GFX8-NEXT: v_sub_f32_e32 v1, v1, v5 +; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 +; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc +; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2 +; GFX8-NEXT: v_add_f32_e32 v0, v0, v7 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5] ; GFX8-NEXT: v_exp_f32_e32 v0, v0 +; GFX8-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX8-NEXT: v_exp_f32_e32 v1, v1 +; GFX8-NEXT: v_not_b32_e32 v4, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5] +; GFX8-NEXT: v_ldexp_f32 v1, v1, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_v2f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v4, 0x800000 +; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4 +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4 +; GFX9-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; GFX9-NEXT: v_ldexp_f32 v0, v0, v5 +; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4 ; GFX9-NEXT: v_log_f32_e32 v0, v0 +; GFX9-NEXT: v_ldexp_f32 v1, v1, v4 ; GFX9-NEXT: v_log_f32_e32 v1, v1 -; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 -; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 +; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6 +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5] +; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 +; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 +; GFX9-NEXT: v_sub_f32_e32 v1, v1, v5 +; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000 +; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc +; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2 +; GFX9-NEXT: v_add_f32_e32 v0, v0, v7 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5] ; GFX9-NEXT: v_exp_f32_e32 v0, v0 +; GFX9-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_exp_f32_e32 v1, v1 +; GFX9-NEXT: v_not_b32_e32 v4, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5] +; GFX9-NEXT: v_ldexp_f32 v1, v1, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_v2f32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, v1 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v4 +; GFX10-NEXT: v_ldexp_f32 v1, v1, v5 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_log_f32_e32 v1, v1 -; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 -; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 +; GFX10-NEXT: v_sub_f32_e32 v0, v0, v4 +; GFX10-NEXT: v_sub_f32_e32 v1, v1, v5 +; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 +; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v1 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s4 +; GFX10-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s4 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v1, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX10-NEXT: v_ldexp_f32 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_v2f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_log_f32_e32 v0, v0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, v1 +; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ldexp_f32 v1, v1, v5 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0 ; GFX11-NEXT: v_log_f32_e32 v1, v1 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v0, v2, v0 :: v_dual_mul_dx9_zero_f32 v1, v3, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_exp_f32_e32 v0, v0 +; GFX11-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v4, 5, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_ldexp_f32 v0, v0, v4 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo +; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_log_f32_e32 v0, v0 +; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0 +; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) +; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3 +; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v1, v1 +; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo +; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) +; GFX11-NEXT: v_ldexp_f32 v1, v1, v3 +; GFX11-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_exp_f32_e32 v0, v0 +; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) +; GFX11-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) ret <2 x float> %pow @@ -812,43 +1019,117 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) { ; GFX6-LABEL: v_pow_f32_fabs_lhs: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_log_f32_e64 v0, |v0| -; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 +;... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/210102 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
