================
@@ -264,35 +267,40 @@ let RegAltNameIndices = [ABIRegAltName] in {
}
}
-def XLenVT : ValueTypeByHwMode<[RV32, RV64],
- [i32, i64]>;
+def XLenVT : ValueTypeByHwMode<[RV32I, RV64I, RV32Y, RV64Y],
+ [i32, i64, i32, i64]>;
defvar XLenPairVT = untyped;
// Allow f64 in GPR for ZDINX on RV64.
-def XLenFVT : ValueTypeByHwMode<[RV64],
- [f64]>;
-def XLenPairFVT : ValueTypeByHwMode<[RV32],
- [f64]>;
-def XLenPairVecI8VT : ValueTypeByHwMode<[RV32],
+def XLenFVT : ValueTypeByHwMode<[DefaultMode, RV64I, RV64Y],
+ [/*XLen*/i32, f64, f64]>;
+def XLenPairFVT : ValueTypeByHwMode<[RV32I, RV32Y],
+ [f64, f64]>;
+def XLenPairVecI8VT : ValueTypeByHwMode<[DefaultMode],
[v8i8]>;
-def XLenPairVecI16VT : ValueTypeByHwMode<[RV32],
+def XLenPairVecI16VT : ValueTypeByHwMode<[DefaultMode],
[v4i16]>;
-def XLenPairVecI32VT : ValueTypeByHwMode<[RV32],
+def XLenPairVecI32VT : ValueTypeByHwMode<[DefaultMode],
[v2i32]>;
----------------
arichardson wrote:
I think this should actually be RV32I, RV32Y but it's been quite a while since
I originally made this change so I'll have to double check. These aren't used
by RVY yet so I just made the minimal changes to keep tablegen happy. I'll
update this to do the right thing.
https://github.com/llvm/llvm-project/pull/177073
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