https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/210100
>From 3b0dd85a530de0ccca429dbc8b74ebea9f30927f Mon Sep 17 00:00:00 2001 From: Petar Avramovic <[email protected]> Date: Thu, 16 Jul 2026 18:17:21 +0200 Subject: [PATCH] GlobalISel: Use extended LLTs in extract lowering --- .../CodeGen/GlobalISel/LegalizerHelper.cpp | 2 +- .../CodeGen/AMDGPU/GlobalISel/global-value.ll | 8 +- .../GlobalISel/legalize-addrspacecast.mir | 24 ++--- .../AMDGPU/GlobalISel/legalize-extract.mir | 4 +- .../codegen-prepare-addrspacecast-non-null.ll | 89 +++++++++++++------ 5 files changed, 79 insertions(+), 48 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index f5cc27fcac60c..63422f5da51a2 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -9734,7 +9734,7 @@ LegalizerHelper::lowerExtract(MachineInstr &MI) { Register ResultReg = DstReg; if (DstTy.isPointer()) ResultReg = - MRI.createGenericVirtualRegister(LLT::scalar(DstTy.getSizeInBits())); + MRI.createGenericVirtualRegister(LLT::integer(DstTy.getSizeInBits())); if (Offset == 0) MIRBuilder.buildTrunc(ResultReg, SrcReg); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll index 1e804a76532fc..ee34c43485da0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll @@ -143,8 +143,8 @@ define ptr addrspace(6) @external_constant32_got() { ; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32, target-flags(amdgpu-gotprel32-hi) @external_constant32, implicit-def $scc ; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4) ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD]](p4) - ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32) + ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32) ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6) ; GCN-NEXT: SI_RETURN implicit $vgpr0 ; @@ -162,8 +162,8 @@ define ptr addrspace(6) @internal_constant32_pcrel() { ; GCN: bb.1 (%ir-block.0): ; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32, target-flags(amdgpu-rel32-hi) @internal_constant32, implicit-def $scc ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[SI_PC_ADD_REL_OFFSET]](p4) - ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32) + ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32) ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6) ; GCN-NEXT: SI_RETURN implicit $vgpr0 ; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir index 5031f14637848..f6fcff54d2e8a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir @@ -187,8 +187,8 @@ body: | ; GCN-NEXT: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 -1 ; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) - ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[TRUNC]](s32) + ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[TRUNC]](i32) ; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]] ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]] ; GCN-NEXT: $vgpr0 = COPY [[SELECT]](p5) @@ -258,8 +258,8 @@ body: | ; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 ; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) - ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32) + ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32) ; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]] ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]] ; GCN-NEXT: $vgpr0 = COPY [[SELECT]](p3) @@ -331,13 +331,13 @@ body: | ; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 ; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV]](p0) - ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32) + ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32) ; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]] ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]] ; GCN-NEXT: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV1]](p0) - ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT1]](s64) - ; GCN-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](s32) + ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT1]](s64) + ; GCN-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](i32) ; GCN-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C1]] ; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[INTTOPTR1]], [[C]] ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[SELECT]](p3), [[SELECT1]](p3) @@ -419,8 +419,8 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1 ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p4) - ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32) + ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32) ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6) %0:_(p4) = COPY $vgpr0_vgpr1 %1:_(p6) = G_ADDRSPACE_CAST %0 @@ -478,8 +478,8 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) - ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](s32) + ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32) ; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6) %0:_(p0) = COPY $vgpr0_vgpr1 %1:_(p6) = G_ADDRSPACE_CAST %0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir index 9841a2bac74d0..ef6699139ca7d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir @@ -1429,8 +1429,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0) - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) - ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32) + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64) + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32) ; CHECK-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3) %0:_(p0) = COPY $vgpr0_vgpr1 %1:_(p3) = G_EXTRACT %0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll b/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll index 70c2975dd2988..c87a7fba94ab3 100644 --- a/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll +++ b/llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -mtriple=amdgpu-- -amdgpu-codegenprepare -S < %s | FileCheck -check-prefix=OPT %s ; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s --check-prefixes=ASM,DAGISEL-ASM -; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -global-isel -global-isel-abort=2 < %s | FileCheck %s --check-prefixes=ASM,GISEL-ASM +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -global-isel < %s | FileCheck %s --check-prefixes=ASM,GISEL-ASM ; Tests that we can avoid nullptr checks for addrspacecasts from/to priv/local. ; @@ -318,34 +318,65 @@ define void @recursive_phis(i1 %cond, ptr addrspace(5) %ptr) { ; OPT: [[END]]: ; OPT-NEXT: ret void ; -; ASM-LABEL: recursive_phis: -; ASM: ; %bb.0: ; %entry -; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ASM-NEXT: v_and_b32_e32 v0, 1, v0 -; ASM-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; ASM-NEXT: v_lshrrev_b32_e64 v0, 6, s32 -; ASM-NEXT: s_and_saveexec_b64 s[4:5], vcc -; ASM-NEXT: ; %bb.1: ; %then -; ASM-NEXT: v_and_b32_e32 v0, 0xffff, v1 -; ASM-NEXT: ; %bb.2: ; %finallyendcf.split -; ASM-NEXT: s_or_b64 exec, exec, s[4:5] -; ASM-NEXT: s_mov_b64 s[4:5], src_private_base -; ASM-NEXT: s_xor_b64 s[8:9], vcc, -1 -; ASM-NEXT: s_mov_b64 s[6:7], 0 -; ASM-NEXT: v_mov_b32_e32 v2, 7 -; ASM-NEXT: .LBB11_3: ; %finally -; ASM-NEXT: ; =>This Inner Loop Header: Depth=1 -; ASM-NEXT: s_and_b64 s[10:11], exec, s[8:9] -; ASM-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] -; ASM-NEXT: v_mov_b32_e32 v1, s5 -; ASM-NEXT: flat_store_dword v[0:1], v2 -; ASM-NEXT: s_waitcnt vmcnt(0) -; ASM-NEXT: s_andn2_b64 exec, exec, s[6:7] -; ASM-NEXT: s_cbranch_execnz .LBB11_3 -; ASM-NEXT: ; %bb.4: ; %end -; ASM-NEXT: s_or_b64 exec, exec, s[6:7] -; ASM-NEXT: s_waitcnt lgkmcnt(0) -; ASM-NEXT: s_setpc_b64 s[30:31] +; DAGISEL-ASM-LABEL: recursive_phis: +; DAGISEL-ASM: ; %bb.0: ; %entry +; DAGISEL-ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; DAGISEL-ASM-NEXT: v_and_b32_e32 v0, 1, v0 +; DAGISEL-ASM-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; DAGISEL-ASM-NEXT: v_lshrrev_b32_e64 v0, 6, s32 +; DAGISEL-ASM-NEXT: s_and_saveexec_b64 s[4:5], vcc +; DAGISEL-ASM-NEXT: ; %bb.1: ; %then +; DAGISEL-ASM-NEXT: v_and_b32_e32 v0, 0xffff, v1 +; DAGISEL-ASM-NEXT: ; %bb.2: ; %finallyendcf.split +; DAGISEL-ASM-NEXT: s_or_b64 exec, exec, s[4:5] +; DAGISEL-ASM-NEXT: s_mov_b64 s[4:5], src_private_base +; DAGISEL-ASM-NEXT: s_xor_b64 s[8:9], vcc, -1 +; DAGISEL-ASM-NEXT: s_mov_b64 s[6:7], 0 +; DAGISEL-ASM-NEXT: v_mov_b32_e32 v2, 7 +; DAGISEL-ASM-NEXT: .LBB11_3: ; %finally +; DAGISEL-ASM-NEXT: ; =>This Inner Loop Header: Depth=1 +; DAGISEL-ASM-NEXT: s_and_b64 s[10:11], exec, s[8:9] +; DAGISEL-ASM-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] +; DAGISEL-ASM-NEXT: v_mov_b32_e32 v1, s5 +; DAGISEL-ASM-NEXT: flat_store_dword v[0:1], v2 +; DAGISEL-ASM-NEXT: s_waitcnt vmcnt(0) +; DAGISEL-ASM-NEXT: s_andn2_b64 exec, exec, s[6:7] +; DAGISEL-ASM-NEXT: s_cbranch_execnz .LBB11_3 +; DAGISEL-ASM-NEXT: ; %bb.4: ; %end +; DAGISEL-ASM-NEXT: s_or_b64 exec, exec, s[6:7] +; DAGISEL-ASM-NEXT: s_waitcnt lgkmcnt(0) +; DAGISEL-ASM-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-ASM-LABEL: recursive_phis: +; GISEL-ASM: ; %bb.0: ; %entry +; GISEL-ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-ASM-NEXT: v_and_b32_e32 v0, 1, v0 +; GISEL-ASM-NEXT: s_mov_b64 s[4:5], exec +; GISEL-ASM-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GISEL-ASM-NEXT: s_lshr_b32 s6, s32, 6 +; GISEL-ASM-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] +; GISEL-ASM-NEXT: v_mov_b32_e32 v0, s6 +; GISEL-ASM-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GISEL-ASM-NEXT: ; %bb.1: ; %then +; GISEL-ASM-NEXT: v_and_b32_e32 v0, 0xffff, v1 +; GISEL-ASM-NEXT: ; %bb.2: ; %finallyendcf.split +; GISEL-ASM-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-ASM-NEXT: s_mov_b64 s[8:9], src_private_base +; GISEL-ASM-NEXT: s_mov_b64 s[6:7], 0 +; GISEL-ASM-NEXT: v_mov_b32_e32 v1, s9 +; GISEL-ASM-NEXT: v_mov_b32_e32 v2, 7 +; GISEL-ASM-NEXT: .LBB11_3: ; %finally +; GISEL-ASM-NEXT: ; =>This Inner Loop Header: Depth=1 +; GISEL-ASM-NEXT: s_and_b64 s[8:9], exec, s[4:5] +; GISEL-ASM-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7] +; GISEL-ASM-NEXT: flat_store_dword v[0:1], v2 +; GISEL-ASM-NEXT: s_waitcnt vmcnt(0) +; GISEL-ASM-NEXT: s_andn2_b64 exec, exec, s[6:7] +; GISEL-ASM-NEXT: s_cbranch_execnz .LBB11_3 +; GISEL-ASM-NEXT: ; %bb.4: ; %end +; GISEL-ASM-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-ASM-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-ASM-NEXT: s_setpc_b64 s[30:31] entry: %alloca = alloca i8, addrspace(5) br i1 %cond, label %then, label %else _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
