https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/209420
>From bf5ad3b324ff511ecc67ecf14c25cddabf9c7aa1 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang <[email protected]> Date: Tue, 14 Jul 2026 17:56:49 +0800 Subject: [PATCH 1/5] clang-format Created using spr 1.3.6-beta.1 --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 9208762e8d1fe..0e69533f56a50 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -3736,8 +3736,8 @@ static bool isRegRegScaleLoadOrStore(SDNode *User, SDValue Add, return false; EVT VT = cast<MemSDNode>(User)->getMemoryVT(); if (!(VT.isScalarInteger() && - (Subtarget.hasStdExtZilx() || - Subtarget.hasVendorXTHeadMemIdx() || Subtarget.hasVendorXqcisls())) && + (Subtarget.hasStdExtZilx() || Subtarget.hasVendorXTHeadMemIdx() || + Subtarget.hasVendorXqcisls())) && !((VT == MVT::f32 || VT == MVT::f64) && Subtarget.hasVendorXTHeadFMemIdx())) return false; >From ddc4fe1cd521bff676fcf361ab67acc72ad1671f Mon Sep 17 00:00:00 2001 From: Pengcheng Wang <[email protected]> Date: Wed, 15 Jul 2026 14:49:45 +0800 Subject: [PATCH 2/5] Increase Complexity Created using spr 1.3.6-beta.1 --- llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td index c7247efed0f4c..7c12cd63f99d0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td @@ -86,10 +86,11 @@ def LXD_S_UW : IndexedLoad<0b101, 0b11, 0, "lxd.s.uw">, } // Predicates = [HasStdExtZilx, IsRV64] class AddrRegReg<int N> - : ComplexPattern<iPTR, 2, "SelectAddrRegRegFixedScale<"#N#">">; + : ComplexPattern<iPTR, 2, "SelectAddrRegRegFixedScale<"#N#">", + [], [], !add(10, N)>; class AddrRegZextReg<int N> : ComplexPattern<i64, 2, "SelectAddrRegZextRegFixedScale<"#N#", 32>", - [], [], 10>; + [], [], !add(20, N)>; def AddrRegReg0 : AddrRegReg<0>; def AddrRegReg1 : AddrRegReg<1>; >From 210e1a40980749a2f028c26f6fa863391f1e62be Mon Sep 17 00:00:00 2001 From: Pengcheng Wang <[email protected]> Date: Wed, 15 Jul 2026 14:58:14 +0800 Subject: [PATCH 3/5] Add more tests Created using spr 1.3.6-beta.1 --- llvm/test/CodeGen/RISCV/zilx.ll | 279 ++++++++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/zilx.ll b/llvm/test/CodeGen/RISCV/zilx.ll index 3a27d801230a7..5ec14ca429a95 100644 --- a/llvm/test/CodeGen/RISCV/zilx.ll +++ b/llvm/test/CodeGen/RISCV/zilx.ll @@ -968,3 +968,282 @@ define i64 @lxd_s_uw(ptr %a, i32 %b) { %3 = load i64, ptr %2, align 8 ret i64 %3 } + +;------------------------------------------------------------------------------ +; Load with a shift amount that doesn't match the access size +; +; The scaled forms require the index shift amount to match log2 of the access +; size. When the shift is smaller or larger than the access size the scaled +; forms can't be used: the shift is materialized separately, but the base+index +; add can still fold into the unscaled index load. +;------------------------------------------------------------------------------ + +; i8 access with the index scaled by 2 (larger than the access size). +define zeroext i8 @lxbu_shl_too_large(ptr %a, iXLen %b) { +; RV32-LABEL: lxbu_shl_too_large: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 2 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: lbu a0, 0(a0) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxbu_shl_too_large: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: slli a1, a1, 2 +; RV32-ZILX-NEXT: lxbu a0, (a0), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxbu_shl_too_large: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 2 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: lbu a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxbu_shl_too_large: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 2 +; RV64-ZILX-NEXT: lxbu a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = getelementptr i32, ptr %a, iXLen %b + %2 = load i8, ptr %1, align 1 + ret i8 %2 +} + +; i16 access with the index scaled by 2 (larger than the access size). +define signext i16 @lxh_s_shl_too_large(ptr %a, iXLen %b) { +; RV32-LABEL: lxh_s_shl_too_large: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 2 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: lh a0, 0(a0) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxh_s_shl_too_large: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: slli a1, a1, 2 +; RV32-ZILX-NEXT: lxh a0, (a0), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxh_s_shl_too_large: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 2 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: lh a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxh_s_shl_too_large: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 2 +; RV64-ZILX-NEXT: lxh a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = getelementptr i32, ptr %a, iXLen %b + %2 = load i16, ptr %1, align 2 + ret i16 %2 +} + +; i32 access with the index scaled by 1 (smaller than the access size). +define i32 @lxw_s_shl_too_small(ptr %a, iXLen %b) { +; RV32-LABEL: lxw_s_shl_too_small: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 1 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: lw a0, 0(a0) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxw_s_shl_too_small: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: slli a1, a1, 1 +; RV32-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxw_s_shl_too_small: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 1 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: lw a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxw_s_shl_too_small: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 1 +; RV64-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = getelementptr i16, ptr %a, iXLen %b + %2 = load i32, ptr %1, align 4 + ret i32 %2 +} + +; i32 access with the index scaled by 3 (larger than the access size). +define i32 @lxw_s_shl_too_large(ptr %a, iXLen %b) { +; RV32-LABEL: lxw_s_shl_too_large: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: lw a0, 0(a0) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxw_s_shl_too_large: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: slli a1, a1, 3 +; RV32-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxw_s_shl_too_large: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 3 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: lw a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxw_s_shl_too_large: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 3 +; RV64-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = getelementptr i64, ptr %a, iXLen %b + %2 = load i32, ptr %1, align 4 + ret i32 %2 +} + +; i64 access with the index scaled by 2 (smaller than the access size). +define i64 @lxd_s_shl_too_small(ptr %a, iXLen %b) { +; RV32-LABEL: lxd_s_shl_too_small: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 2 +; RV32-NEXT: add a1, a0, a1 +; RV32-NEXT: lw a0, 0(a1) +; RV32-NEXT: lw a1, 4(a1) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxd_s_shl_too_small: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: addi a2, a0, 4 +; RV32-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV32-ZILX-NEXT: lxw.s a1, (a2), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxd_s_shl_too_small: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 2 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: ld a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxd_s_shl_too_small: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 2 +; RV64-ZILX-NEXT: lxd a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = getelementptr i32, ptr %a, iXLen %b + %2 = load i64, ptr %1, align 8 + ret i64 %2 +} + +; i16 access with the zero-extended index scaled by 2 (larger than the access +; size). +define signext i16 @lxh_s_uw_shl_too_large(ptr %a, i32 %b) { +; RV32-LABEL: lxh_s_uw_shl_too_large: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 2 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: lh a0, 0(a0) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxh_s_uw_shl_too_large: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: slli a1, a1, 2 +; RV32-ZILX-NEXT: lxh a0, (a0), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxh_s_uw_shl_too_large: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 32 +; RV64-NEXT: srli a1, a1, 30 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: lh a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxh_s_uw_shl_too_large: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 32 +; RV64-ZILX-NEXT: srli a1, a1, 30 +; RV64-ZILX-NEXT: lxh a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = zext i32 %b to i64 + %2 = getelementptr i32, ptr %a, i64 %1 + %3 = load i16, ptr %2, align 2 + ret i16 %3 +} + +; i32 access with the zero-extended index scaled by 1 (smaller than the access +; size). +define i32 @lxw_s_uw_shl_too_small(ptr %a, i32 %b) { +; RV32-LABEL: lxw_s_uw_shl_too_small: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 1 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: lw a0, 0(a0) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxw_s_uw_shl_too_small: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: slli a1, a1, 1 +; RV32-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxw_s_uw_shl_too_small: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 32 +; RV64-NEXT: srli a1, a1, 31 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: lw a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxw_s_uw_shl_too_small: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 32 +; RV64-ZILX-NEXT: srli a1, a1, 31 +; RV64-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = zext i32 %b to i64 + %2 = getelementptr i16, ptr %a, i64 %1 + %3 = load i32, ptr %2, align 4 + ret i32 %3 +} + +; i32 access with the zero-extended index scaled by 3 (larger than the access +; size). +define i32 @lxw_s_uw_shl_too_large(ptr %a, i32 %b) { +; RV32-LABEL: lxw_s_uw_shl_too_large: +; RV32: # %bb.0: +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: lw a0, 0(a0) +; RV32-NEXT: ret +; +; RV32-ZILX-LABEL: lxw_s_uw_shl_too_large: +; RV32-ZILX: # %bb.0: +; RV32-ZILX-NEXT: slli a1, a1, 3 +; RV32-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZILX-NEXT: ret +; +; RV64-LABEL: lxw_s_uw_shl_too_large: +; RV64: # %bb.0: +; RV64-NEXT: slli a1, a1, 32 +; RV64-NEXT: srli a1, a1, 29 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: lw a0, 0(a0) +; RV64-NEXT: ret +; +; RV64-ZILX-LABEL: lxw_s_uw_shl_too_large: +; RV64-ZILX: # %bb.0: +; RV64-ZILX-NEXT: slli a1, a1, 32 +; RV64-ZILX-NEXT: srli a1, a1, 29 +; RV64-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZILX-NEXT: ret + %1 = zext i32 %b to i64 + %2 = getelementptr i64, ptr %a, i64 %1 + %3 = load i32, ptr %2, align 4 + ret i32 %3 +} >From f092d03628360072a4000f1ab5e561d6e5697c3b Mon Sep 17 00:00:00 2001 From: Pengcheng Wang <[email protected]> Date: Thu, 16 Jul 2026 11:51:00 +0800 Subject: [PATCH 4/5] Add comments and change the calculation of complexities Created using spr 1.3.6-beta.1 --- llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td index 900971d282b1b..eb9f124dcc5cd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td @@ -85,12 +85,25 @@ def LXD_S_UW : IndexedLoad<0b101, 0b11, 0, "lxd.s.uw">, Sched<[WriteLDD, ReadMemBase, ReadMemBase]>; } // Predicates = [HasStdExtZilx, IsRV64] +// The complexities below are chosen to give the indexed loads a strict +// priority over the plain reg+imm loads and to encode which form is the more +// specific match. Without an explicit complexity these patterns tie with the +// base L{B,H,W,D}[U] patterns (which also match a "reg + reg" address as +// base+0) and, being listed later, would never be selected. The required +// ordering is: +// base L* < scale-0 (unscaled) Zilx < scaled Zilx +// For a given load only the scale-0 form (which leaves the shift as a separate +// slli) and the exactly-matching scaled form can compete, so a scaled load +// only needs to outrank its own unscaled form; distinct non-zero scales never +// compete for the same node. class AddrRegReg<int N> : ComplexPattern<iPTR, 2, "SelectAddrRegRegFixedScale<"#N#">", - [], [], !add(10, N)>; + [], [], !if(!eq(N, 0), 10, 11)>; +// The zero-extended-index forms additionally fold the zext, so they are the +// most specific match and must outrank the plain AddrRegReg forms above. class AddrRegZextReg<int N> : ComplexPattern<i64, 2, "SelectAddrRegZextRegFixedScale<"#N#", 32>", - [], [], !add(20, N)>; + [], [], !if(!eq(N, 0), 20, 21)>; def AddrRegReg0 : AddrRegReg<0>; def AddrRegReg1 : AddrRegReg<1>; >From d0047ee92da6a64e256f9864ab293ecc9e99cea2 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang <[email protected]> Date: Fri, 17 Jul 2026 11:21:44 +0800 Subject: [PATCH 5/5] Add RUNs with zba and zba+zilx Created using spr 1.3.6-beta.1 --- llvm/test/CodeGen/RISCV/zilx.ll | 912 ++++++++++++++++++++++++++++++++ 1 file changed, 912 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/zilx.ll b/llvm/test/CodeGen/RISCV/zilx.ll index 5ec14ca429a95..0f10230077388 100644 --- a/llvm/test/CodeGen/RISCV/zilx.ll +++ b/llvm/test/CodeGen/RISCV/zilx.ll @@ -3,10 +3,18 @@ ; RUN: | FileCheck -check-prefix=RV32 %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+experimental-zilx -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=RV32-ZILX %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zba -verify-machineinstrs \ +; RUN: | FileCheck -check-prefix=RV32-ZBA %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zba,+experimental-zilx -verify-machineinstrs \ +; RUN: | FileCheck -check-prefix=RV32-ZBA-ZILX %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=RV64 %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+experimental-zilx -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=RV64-ZILX %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zba -verify-machineinstrs \ +; RUN: | FileCheck -check-prefix=RV64-ZBA %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zba,+experimental-zilx -verify-machineinstrs \ +; RUN: | FileCheck -check-prefix=RV64-ZBA-ZILX %s ;------------------------------------------------------------------------------ ; Unscaled Load @@ -24,6 +32,17 @@ define i8 @lxb_anyext(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxb a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxb_anyext: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lbu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxb_anyext: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxb a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxb_anyext: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -34,6 +53,17 @@ define i8 @lxb_anyext(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxb a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxb_anyext: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: lbu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxb_anyext: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxb a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i8, ptr %1, align 1 ret i8 %2 @@ -51,6 +81,17 @@ define i32 @lxb(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxb a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxb: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lb a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxb: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxb a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxb: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -61,6 +102,17 @@ define i32 @lxb(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxb a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxb: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: lb a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxb: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxb a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i8, ptr %1, align 1 %3 = sext i8 %2 to i32 @@ -79,6 +131,17 @@ define i8 @lxb_uw_anyext(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxb a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxb_uw_anyext: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lbu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxb_uw_anyext: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxb a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxb_uw_anyext: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -91,6 +154,17 @@ define i8 @lxb_uw_anyext(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxb.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxb_uw_anyext: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lbu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxb_uw_anyext: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxb.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i8, ptr %2, align 1 @@ -109,6 +183,17 @@ define i32 @lxb_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxb a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxb_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lb a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxb_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxb a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxb_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -121,6 +206,17 @@ define i32 @lxb_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxb.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxb_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lb a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxb_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxb.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i8, ptr %2, align 1 @@ -140,6 +236,17 @@ define i32 @lxbu(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxbu a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxbu: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lbu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxbu: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxbu a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxbu: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -150,6 +257,17 @@ define i32 @lxbu(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxbu a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxbu: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: lbu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxbu: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxbu a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i8, ptr %1, align 1 %3 = zext i8 %2 to i32 @@ -168,6 +286,17 @@ define i32 @lxbu_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxbu a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxbu_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lbu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxbu_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxbu a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxbu_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -180,6 +309,17 @@ define i32 @lxbu_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxbu.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxbu_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lbu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxbu_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxbu.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i8, ptr %2, align 1 @@ -199,6 +339,17 @@ define i16 @lxh(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxh a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxh a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -209,6 +360,17 @@ define i16 @lxh(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxh a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxh a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i16, ptr %1, align 2 ret i16 %2 @@ -226,6 +388,17 @@ define i16 @lxh_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxh a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxh a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -238,6 +411,17 @@ define i16 @lxh_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxh.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxh.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i16, ptr %2, align 2 @@ -256,6 +440,17 @@ define i32 @lxhu(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxhu a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxhu: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lhu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxhu: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxhu a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxhu: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -266,6 +461,17 @@ define i32 @lxhu(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxhu a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxhu: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: lhu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxhu: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxhu a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i16, ptr %1, align 2 %3 = zext i16 %2 to i32 @@ -284,6 +490,17 @@ define i32 @lxhu_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxhu a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxhu_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lhu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxhu_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxhu a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxhu_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -296,6 +513,17 @@ define i32 @lxhu_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxhu.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxhu_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lhu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxhu_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxhu.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i16, ptr %2, align 2 @@ -315,6 +543,17 @@ define i32 @lxw(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxw a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -325,6 +564,17 @@ define i32 @lxw(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i32, ptr %1, align 4 ret i32 %2 @@ -342,6 +592,17 @@ define i32 @lxw_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxw a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -354,6 +615,17 @@ define i32 @lxw_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxw.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxw.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i32, ptr %2, align 4 @@ -374,6 +646,19 @@ define i64 @lxwu(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: li a1, 0 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxwu: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: li a1, 0 +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxwu: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: li a1, 0 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxwu: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -384,6 +669,17 @@ define i64 @lxwu(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxwu a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxwu: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: lwu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxwu: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxwu a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i32, ptr %1, align 4 %3 = zext i32 %2 to i64 @@ -404,6 +700,19 @@ define i64 @lxwu_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: li a1, 0 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxwu_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a0, a0, a1 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: li a1, 0 +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxwu_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: li a1, 0 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxwu_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -416,6 +725,17 @@ define i64 @lxwu_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxwu.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxwu_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lwu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxwu_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxwu.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i32, ptr %2, align 4 @@ -438,6 +758,20 @@ define i64 @lxd(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lw a1, 4(a1) ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxd: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a1, a0, a1 +; RV32-ZBA-NEXT: lw a0, 0(a1) +; RV32-ZBA-NEXT: lw a1, 4(a1) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxd: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: add a1, a0, a1 +; RV32-ZBA-ZILX-NEXT: lw a0, 0(a1) +; RV32-ZBA-ZILX-NEXT: lw a1, 4(a1) +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxd: ; RV64: # %bb.0: ; RV64-NEXT: add a0, a0, a1 @@ -448,6 +782,17 @@ define i64 @lxd(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxd a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxd: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add a0, a0, a1 +; RV64-ZBA-NEXT: ld a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxd: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxd a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i8, ptr %a, iXLen %b %2 = load i64, ptr %1, align 8 ret i64 %2 @@ -468,6 +813,20 @@ define i64 @lxd_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lw a1, 4(a1) ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxd_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: add a1, a0, a1 +; RV32-ZBA-NEXT: lw a0, 0(a1) +; RV32-ZBA-NEXT: lw a1, 4(a1) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxd_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: add a1, a0, a1 +; RV32-ZBA-ZILX-NEXT: lw a0, 0(a1) +; RV32-ZBA-ZILX-NEXT: lw a1, 4(a1) +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxd_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -480,6 +839,17 @@ define i64 @lxd_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxd.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxd_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: add.uw a0, a1, a0 +; RV64-ZBA-NEXT: ld a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxd_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxd.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i8, ptr %a, i64 %1 %3 = load i64, ptr %2, align 8 @@ -503,6 +873,17 @@ define i16 @lxh_s_anyext(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxh.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh_s_anyext: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh_s_anyext: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxh.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh_s_anyext: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 1 @@ -514,6 +895,17 @@ define i16 @lxh_s_anyext(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxh.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh_s_anyext: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add a0, a1, a0 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh_s_anyext: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxh.s a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i16, ptr %a, iXLen %b %2 = load i16, ptr %1, align 2 ret i16 %2 @@ -532,6 +924,17 @@ define i32 @lxh_s(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxh.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh_s: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh_s: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxh.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh_s: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 1 @@ -543,6 +946,17 @@ define i32 @lxh_s(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxh.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh_s: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add a0, a1, a0 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh_s: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxh.s a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i16, ptr %a, iXLen %b %2 = load i16, ptr %1, align 2 %3 = sext i16 %2 to i32 @@ -562,6 +976,17 @@ define i16 @lxh_s_uw_anyext(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxh.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh_s_uw_anyext: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh_s_uw_anyext: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxh.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh_s_uw_anyext: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -574,6 +999,17 @@ define i16 @lxh_s_uw_anyext(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxh.s.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh_s_uw_anyext: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh_s_uw_anyext: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxh.s.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i16, ptr %a, i64 %1 %3 = load i16, ptr %2, align 2 @@ -593,6 +1029,17 @@ define i32 @lxh_s_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxh.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh_s_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh_s_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxh.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh_s_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -605,6 +1052,17 @@ define i32 @lxh_s_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxh.s.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh_s_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh_s_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxh.s.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i16, ptr %a, i64 %1 %3 = load i16, ptr %2, align 2 @@ -625,6 +1083,17 @@ define i32 @lxhu_s(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxhu.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxhu_s: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lhu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxhu_s: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxhu.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxhu_s: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 1 @@ -636,6 +1105,17 @@ define i32 @lxhu_s(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxhu.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxhu_s: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add a0, a1, a0 +; RV64-ZBA-NEXT: lhu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxhu_s: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxhu.s a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i16, ptr %a, iXLen %b %2 = load i16, ptr %1, align 2 %3 = zext i16 %2 to i32 @@ -655,6 +1135,17 @@ define i32 @lxhu_s_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxhu.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxhu_s_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lhu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxhu_s_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxhu.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxhu_s_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -667,6 +1158,17 @@ define i32 @lxhu_s_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxhu.s.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxhu_s_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lhu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxhu_s_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxhu.s.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i16, ptr %a, i64 %1 %3 = load i16, ptr %2, align 2 @@ -687,6 +1189,17 @@ define i32 @lxw_s_anyext(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxw.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s_anyext: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s_anyext: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s_anyext: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 2 @@ -698,6 +1211,17 @@ define i32 @lxw_s_anyext(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxw.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s_anyext: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s_anyext: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i32, ptr %a, iXLen %b %2 = load i32, ptr %1, align 4 ret i32 %2 @@ -718,6 +1242,19 @@ define i64 @lxw_s(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: srai a1, a0, 31 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: srai a1, a0, 31 +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: srai a1, a0, 31 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 2 @@ -729,6 +1266,17 @@ define i64 @lxw_s(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxw.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i32, ptr %a, iXLen %b %2 = load i32, ptr %1, align 4 %3 = sext i32 %2 to i64 @@ -748,6 +1296,17 @@ define i32 @lxw_s_uw_anyext(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxw.s a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s_uw_anyext: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s_uw_anyext: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s_uw_anyext: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -760,6 +1319,17 @@ define i32 @lxw_s_uw_anyext(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxw.s.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s_uw_anyext: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s_uw_anyext: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxw.s.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i32, ptr %a, i64 %1 %3 = load i32, ptr %2, align 4 @@ -781,6 +1351,19 @@ define i64 @lxw_s_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: srai a1, a0, 31 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: srai a1, a0, 31 +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: srai a1, a0, 31 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -793,6 +1376,17 @@ define i64 @lxw_s_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxw.s.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxw.s.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i32, ptr %a, i64 %1 %3 = load i32, ptr %2, align 4 @@ -815,6 +1409,19 @@ define i64 @lxwu_s(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: li a1, 0 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxwu_s: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: li a1, 0 +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxwu_s: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: li a1, 0 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxwu_s: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 2 @@ -826,6 +1433,17 @@ define i64 @lxwu_s(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxwu.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxwu_s: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add a0, a1, a0 +; RV64-ZBA-NEXT: lwu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxwu_s: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxwu.s a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i32, ptr %a, iXLen %b %2 = load i32, ptr %1, align 4 %3 = zext i32 %2 to i64 @@ -847,6 +1465,19 @@ define i64 @lxwu_s_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: li a1, 0 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxwu_s_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: li a1, 0 +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxwu_s_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: lxw.s a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: li a1, 0 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxwu_s_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -859,6 +1490,17 @@ define i64 @lxwu_s_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxwu.s.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxwu_s_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lwu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxwu_s_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxwu.s.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i32, ptr %a, i64 %1 %3 = load i32, ptr %2, align 4 @@ -883,6 +1525,20 @@ define i64 @lxd_s(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lw a1, 4(a1) ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxd_s: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh3add a1, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a1) +; RV32-ZBA-NEXT: lw a1, 4(a1) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxd_s: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: sh3add a1, a1, a0 +; RV32-ZBA-ZILX-NEXT: lw a0, 0(a1) +; RV32-ZBA-ZILX-NEXT: lw a1, 4(a1) +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxd_s: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 3 @@ -894,6 +1550,17 @@ define i64 @lxd_s(ptr %a, iXLen %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxd.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxd_s: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh3add a0, a1, a0 +; RV64-ZBA-NEXT: ld a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxd_s: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxd.s a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i64, ptr %a, iXLen %b %2 = load i64, ptr %1, align 8 ret i64 %2 @@ -916,6 +1583,20 @@ define i64 @lxd_s_2(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lw a1, 100(a1) ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxd_s_2: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh3add a1, a1, a0 +; RV32-ZBA-NEXT: lw a0, 96(a1) +; RV32-ZBA-NEXT: lw a1, 100(a1) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxd_s_2: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: sh3add a1, a1, a0 +; RV32-ZBA-ZILX-NEXT: lw a0, 96(a1) +; RV32-ZBA-ZILX-NEXT: lw a1, 100(a1) +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxd_s_2: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 3 @@ -928,6 +1609,18 @@ define i64 @lxd_s_2(ptr %a, iXLen %b) { ; RV64-ZILX-NEXT: addi a0, a0, 96 ; RV64-ZILX-NEXT: lxd.s a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxd_s_2: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh3add a0, a1, a0 +; RV64-ZBA-NEXT: ld a0, 96(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxd_s_2: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: sh3add a0, a1, a0 +; RV64-ZBA-ZILX-NEXT: ld a0, 96(a0) +; RV64-ZBA-ZILX-NEXT: ret %1 = add iXLen %b, 12 %2 = getelementptr i64, ptr %a, iXLen %1 %3 = load i64, ptr %2, align 8 @@ -951,6 +1644,20 @@ define i64 @lxd_s_uw(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lw a1, 4(a1) ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxd_s_uw: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh3add a1, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a1) +; RV32-ZBA-NEXT: lw a1, 4(a1) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxd_s_uw: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: sh3add a1, a1, a0 +; RV32-ZBA-ZILX-NEXT: lw a0, 0(a1) +; RV32-ZBA-ZILX-NEXT: lw a1, 4(a1) +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxd_s_uw: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -963,6 +1670,17 @@ define i64 @lxd_s_uw(ptr %a, i32 %b) { ; RV64-ZILX: # %bb.0: ; RV64-ZILX-NEXT: lxd.s.uw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxd_s_uw: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh3add.uw a0, a1, a0 +; RV64-ZBA-NEXT: ld a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxd_s_uw: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: lxd.s.uw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i64, ptr %a, i64 %1 %3 = load i64, ptr %2, align 8 @@ -993,6 +1711,18 @@ define zeroext i8 @lxbu_shl_too_large(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxbu a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxbu_shl_too_large: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lbu a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxbu_shl_too_large: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: slli a1, a1, 2 +; RV32-ZBA-ZILX-NEXT: lxbu a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxbu_shl_too_large: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 2 @@ -1005,6 +1735,18 @@ define zeroext i8 @lxbu_shl_too_large(ptr %a, iXLen %b) { ; RV64-ZILX-NEXT: slli a1, a1, 2 ; RV64-ZILX-NEXT: lxbu a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxbu_shl_too_large: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add a0, a1, a0 +; RV64-ZBA-NEXT: lbu a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxbu_shl_too_large: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli a1, a1, 2 +; RV64-ZBA-ZILX-NEXT: lxbu a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i32, ptr %a, iXLen %b %2 = load i8, ptr %1, align 1 ret i8 %2 @@ -1025,6 +1767,18 @@ define signext i16 @lxh_s_shl_too_large(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxh a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh_s_shl_too_large: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh_s_shl_too_large: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: slli a1, a1, 2 +; RV32-ZBA-ZILX-NEXT: lxh a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh_s_shl_too_large: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 2 @@ -1037,6 +1791,18 @@ define signext i16 @lxh_s_shl_too_large(ptr %a, iXLen %b) { ; RV64-ZILX-NEXT: slli a1, a1, 2 ; RV64-ZILX-NEXT: lxh a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh_s_shl_too_large: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add a0, a1, a0 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh_s_shl_too_large: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli a1, a1, 2 +; RV64-ZBA-ZILX-NEXT: lxh a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i32, ptr %a, iXLen %b %2 = load i16, ptr %1, align 2 ret i16 %2 @@ -1057,6 +1823,18 @@ define i32 @lxw_s_shl_too_small(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxw a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s_shl_too_small: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s_shl_too_small: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: slli a1, a1, 1 +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s_shl_too_small: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 1 @@ -1069,6 +1847,18 @@ define i32 @lxw_s_shl_too_small(ptr %a, iXLen %b) { ; RV64-ZILX-NEXT: slli a1, a1, 1 ; RV64-ZILX-NEXT: lxw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s_shl_too_small: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s_shl_too_small: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli a1, a1, 1 +; RV64-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i16, ptr %a, iXLen %b %2 = load i32, ptr %1, align 4 ret i32 %2 @@ -1089,6 +1879,18 @@ define i32 @lxw_s_shl_too_large(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxw a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s_shl_too_large: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh3add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s_shl_too_large: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: slli a1, a1, 3 +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s_shl_too_large: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 3 @@ -1101,6 +1903,18 @@ define i32 @lxw_s_shl_too_large(ptr %a, iXLen %b) { ; RV64-ZILX-NEXT: slli a1, a1, 3 ; RV64-ZILX-NEXT: lxw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s_shl_too_large: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh3add a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s_shl_too_large: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli a1, a1, 3 +; RV64-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i64, ptr %a, iXLen %b %2 = load i32, ptr %1, align 4 ret i32 %2 @@ -1123,6 +1937,20 @@ define i64 @lxd_s_shl_too_small(ptr %a, iXLen %b) { ; RV32-ZILX-NEXT: lxw.s a1, (a2), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxd_s_shl_too_small: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a1, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a1) +; RV32-ZBA-NEXT: lw a1, 4(a1) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxd_s_shl_too_small: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: sh2add a1, a1, a0 +; RV32-ZBA-ZILX-NEXT: lw a0, 0(a1) +; RV32-ZBA-ZILX-NEXT: lw a1, 4(a1) +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxd_s_shl_too_small: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 2 @@ -1135,6 +1963,18 @@ define i64 @lxd_s_shl_too_small(ptr %a, iXLen %b) { ; RV64-ZILX-NEXT: slli a1, a1, 2 ; RV64-ZILX-NEXT: lxd a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxd_s_shl_too_small: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add a0, a1, a0 +; RV64-ZBA-NEXT: ld a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxd_s_shl_too_small: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli a1, a1, 2 +; RV64-ZBA-ZILX-NEXT: lxd a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = getelementptr i32, ptr %a, iXLen %b %2 = load i64, ptr %1, align 8 ret i64 %2 @@ -1156,6 +1996,18 @@ define signext i16 @lxh_s_uw_shl_too_large(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxh a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxh_s_uw_shl_too_large: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh2add a0, a1, a0 +; RV32-ZBA-NEXT: lh a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxh_s_uw_shl_too_large: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: slli a1, a1, 2 +; RV32-ZBA-ZILX-NEXT: lxh a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxh_s_uw_shl_too_large: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -1170,6 +2022,18 @@ define signext i16 @lxh_s_uw_shl_too_large(ptr %a, i32 %b) { ; RV64-ZILX-NEXT: srli a1, a1, 30 ; RV64-ZILX-NEXT: lxh a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxh_s_uw_shl_too_large: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh2add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lh a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxh_s_uw_shl_too_large: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli.uw a1, a1, 2 +; RV64-ZBA-ZILX-NEXT: lxh a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i32, ptr %a, i64 %1 %3 = load i16, ptr %2, align 2 @@ -1192,6 +2056,18 @@ define i32 @lxw_s_uw_shl_too_small(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxw a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s_uw_shl_too_small: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh1add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s_uw_shl_too_small: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: slli a1, a1, 1 +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s_uw_shl_too_small: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -1206,6 +2082,18 @@ define i32 @lxw_s_uw_shl_too_small(ptr %a, i32 %b) { ; RV64-ZILX-NEXT: srli a1, a1, 31 ; RV64-ZILX-NEXT: lxw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s_uw_shl_too_small: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh1add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s_uw_shl_too_small: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli.uw a1, a1, 1 +; RV64-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i16, ptr %a, i64 %1 %3 = load i32, ptr %2, align 4 @@ -1228,6 +2116,18 @@ define i32 @lxw_s_uw_shl_too_large(ptr %a, i32 %b) { ; RV32-ZILX-NEXT: lxw a0, (a0), a1 ; RV32-ZILX-NEXT: ret ; +; RV32-ZBA-LABEL: lxw_s_uw_shl_too_large: +; RV32-ZBA: # %bb.0: +; RV32-ZBA-NEXT: sh3add a0, a1, a0 +; RV32-ZBA-NEXT: lw a0, 0(a0) +; RV32-ZBA-NEXT: ret +; +; RV32-ZBA-ZILX-LABEL: lxw_s_uw_shl_too_large: +; RV32-ZBA-ZILX: # %bb.0: +; RV32-ZBA-ZILX-NEXT: slli a1, a1, 3 +; RV32-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV32-ZBA-ZILX-NEXT: ret +; ; RV64-LABEL: lxw_s_uw_shl_too_large: ; RV64: # %bb.0: ; RV64-NEXT: slli a1, a1, 32 @@ -1242,6 +2142,18 @@ define i32 @lxw_s_uw_shl_too_large(ptr %a, i32 %b) { ; RV64-ZILX-NEXT: srli a1, a1, 29 ; RV64-ZILX-NEXT: lxw a0, (a0), a1 ; RV64-ZILX-NEXT: ret +; +; RV64-ZBA-LABEL: lxw_s_uw_shl_too_large: +; RV64-ZBA: # %bb.0: +; RV64-ZBA-NEXT: sh3add.uw a0, a1, a0 +; RV64-ZBA-NEXT: lw a0, 0(a0) +; RV64-ZBA-NEXT: ret +; +; RV64-ZBA-ZILX-LABEL: lxw_s_uw_shl_too_large: +; RV64-ZBA-ZILX: # %bb.0: +; RV64-ZBA-ZILX-NEXT: slli.uw a1, a1, 3 +; RV64-ZBA-ZILX-NEXT: lxw a0, (a0), a1 +; RV64-ZBA-ZILX-NEXT: ret %1 = zext i32 %b to i64 %2 = getelementptr i64, ptr %a, i64 %1 %3 = load i32, ptr %2, align 4 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
