https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/218895
>From 4028c1696d88ea6fbad69898f0826f3f933daae3 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Tue, 18 Aug 2026 22:13:49 +0200 Subject: [PATCH] CodeGen: Fix MachineCSE PRE insert point with SUCC_ARGS Hoist to getBlockEndInsertPt() instead of getFirstTerminator(), so a hoisted instruction lands before the SUCC_ARGS cluster rather than inside it. Co-Authored-By: Claude <[email protected]> (Claude Opus 4.8) --- llvm/lib/CodeGen/MachineCSE.cpp | 2 +- .../PowerPC/machine-cse-pre-succ-args.mir | 99 +++++++++++++++++++ 2 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/PowerPC/machine-cse-pre-succ-args.mir diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index 2ac740856c439..3e57f635c515f 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -872,7 +872,7 @@ bool MachineCSEImpl::ProcessBlockPRE(MachineDominatorTree *DT, if (!isProfitableToCSE(NewReg, VReg, CMBB, &MI)) continue; MachineInstr &NewMI = - TII->duplicate(*CMBB, CMBB->getFirstTerminator(), MI); + TII->duplicate(*CMBB, CMBB->getBlockEndInsertPt(), MI); // When hoisting, make sure we don't carry the debug location of // the original instruction, as that's not correct and can cause diff --git a/llvm/test/CodeGen/PowerPC/machine-cse-pre-succ-args.mir b/llvm/test/CodeGen/PowerPC/machine-cse-pre-succ-args.mir new file mode 100644 index 0000000000000..a4baba760e1d2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/machine-cse-pre-succ-args.mir @@ -0,0 +1,99 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc %s -o - -mtriple=powerpc-unknown-unknown -run-pass=machine-cse | FileCheck %s + +# MachineCSE PRE hoists the redundant FDIV into bb.1, which must land before the +# SUCC_ARGS cluster rather than inside it. + +--- | + define void @can_pre() { + entry: + br label %for.body + for.body: + br i1 poison, label %if.then, label %if.else + if.then: + br label %if.end + if.else: + br label %if.end + if.end: + br label %for.body + } +... +--- +name: can_pre +tracksRegLiveness: true +usesBlockArgs: true +body: | + ; CHECK-LABEL: name: can_pre + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $r1, $f1, $f2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprc = COPY $r1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:f8rc = COPY $f1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:f8rc = COPY $f2 + ; CHECK-NEXT: SUCC_ARGS %bb.1, [[COPY1]] + ; CHECK-NEXT: B %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: arguments: %3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $cr0 = CMPLWI [[COPY]], 0 + ; CHECK-NEXT: [[FDIV:%[0-9]+]]:f8rc = nofpexcept FDIV [[COPY1]], [[COPY2]], implicit $rm + ; CHECK-NEXT: SUCC_ARGS %bb.4, %3:f8rc + ; CHECK-NEXT: BCC 44, $cr0, %bb.2 + ; CHECK-NEXT: B %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.then: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SUCC_ARGS %bb.4, [[FDIV]] + ; CHECK-NEXT: B %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.if.else: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SUCC_ARGS %bb.4, [[FDIV]] + ; CHECK-NEXT: B %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.if.end: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: arguments: %6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SUCC_ARGS %bb.1, %6:f8rc + ; CHECK-NEXT: B %bb.1 + bb.0.entry: + successors: %bb.1 + liveins: $r1, $f1, $f2 + %2:gprc = COPY $r1 + %4:f8rc = COPY $f1 + %5:f8rc = COPY $f2 + SUCC_ARGS %bb.1, %4 + B %bb.1 + + bb.1.for.body: + successors: %bb.2, %bb.3 + arguments: %6:f8rc + $cr0 = CMPLWI %2, 0 + SUCC_ARGS %bb.4, %6 + BCC 44, $cr0, %bb.2 + B %bb.3 + + bb.2.if.then: + successors: %bb.4 + %0:f8rc = nofpexcept FDIV %4, %5, implicit $rm + SUCC_ARGS %bb.4, %0 + B %bb.4 + + bb.3.if.else: + successors: %bb.4 + %1:f8rc = nofpexcept FDIV %4, %5, implicit $rm + SUCC_ARGS %bb.4, %1 + B %bb.4 + + bb.4.if.end: + successors: %bb.1 + arguments: %7:f8rc + SUCC_ARGS %bb.1, %7 + B %bb.1 +... _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
