https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/219020
>From dfaad4031cf7cb301dd4f0a1d103432e9ce7b803 Mon Sep 17 00:00:00 2001 From: Chinmay Deshpande <[email protected]> Date: Wed, 26 Aug 2026 15:44:50 -0400 Subject: [PATCH 1/2] [AMDGPU] Movee MaxHWAddreessableLocalMemorySize into TargetParser Change-Id: I5984dca3e76713b551494c7b3f3f892765a9ecf5 --- .../llvm/TargetParser/AMDGPUTargetParser.h | 7 ++++ .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 13 ++------ llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 11 +++++++ .../AMDGPUTargetDefSubArchSpelling.td | 4 +-- .../TargetParser/TargetParserTest.cpp | 32 +++++++++++++++++++ .../TableGen/Basic/AMDGPUTargetDefEmitter.cpp | 3 +- 6 files changed, 56 insertions(+), 14 deletions(-) diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h index b3e40307cc9dd..5d4a87b64f86d 100644 --- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h +++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h @@ -202,6 +202,13 @@ LLVM_ABI unsigned getAddressableNumSGPRs(Triple::SubArchType SubArch); LLVM_ABI unsigned getSGPRAllocGranule(GPUKind AK); LLVM_ABI unsigned getSGPRAllocGranule(Triple::SubArchType SubArch); +/// \returns Maximum LDS in bytes a single work-group can address. This is a +/// fixed hardware cap and does not depend on how many SIMDs a work-group runs +/// on. +LLVM_ABI unsigned getMaxHWAddressableLocalMemorySize(GPUKind AK); +LLVM_ABI unsigned +getMaxHWAddressableLocalMemorySize(Triple::SubArchType SubArch); + /// \returns Number of SIMDs a work-group's waves run on. All four SIMDs of the /// functional block in full-SIMD mode, half of them otherwise. constexpr unsigned getNumWorkGroupSIMDs(bool FullSIMDMode) { diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index a0648da67c06d..4f4a5ff2f246b 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1179,17 +1179,8 @@ unsigned getWavefrontSize(const MCSubtargetInfo &STI) { // Maximum LDS a single work-group can address. This is a fixed HW cap. It does // not depend on how many SIMDs a work-group runs on. static unsigned getMaxHWAddressableLocalMemorySize(const MCSubtargetInfo &STI) { - if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize32768)) - return 32768; - if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize65536)) - return 65536; - if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize163840)) - return 163840; - if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize196608)) - return 196608; - if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize327680)) - return 327680; - return 32768; + return AMDGPU::getMaxHWAddressableLocalMemorySize( + parseArchAMDGCN(STI.getCPU())); } // Total physical size of LDS on the block, in bytes. On targets with diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp index b1450e23604e3..66c793a10dacc 100644 --- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp +++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp @@ -43,6 +43,7 @@ struct GPUInfo { StringTable::Offset FamilyName; StringTable::Offset BaseName; // The canonical device name for a variant. uint8_t MaxWavesPerEU; + uint32_t MaxHWAddressableLocalMemorySize; }; // Per-GPU data for the R600 GPUKinds. @@ -430,6 +431,16 @@ unsigned AMDGPU::getSGPRAllocGranule(Triple::SubArchType SubArch) { return 8; } +unsigned AMDGPU::getMaxHWAddressableLocalMemorySize(GPUKind AK) { + const GPUInfo *Info = getAMDGPUInfo(AK); + return Info ? Info->MaxHWAddressableLocalMemorySize : 32768; +} + +unsigned +AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::SubArchType SubArch) { + return getMaxHWAddressableLocalMemorySize(getGPUKindFromSubArch(SubArch)); +} + unsigned AMDGPU::getMaxWavesPerEU(GPUKind AK) { const GPUInfo *Info = getAMDGPUInfo(AK); return Info ? Info->MaxWavesPerEU : 10; diff --git a/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td b/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td index b0aa8458575c3..f901bdaf9c47c 100644 --- a/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td +++ b/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td @@ -37,8 +37,8 @@ def GFX888_AMAZING : ProcessorModel<"gfx888-amazing", NoSchedModel, []>, // The GPU table: the base GPU has no base name (offset 0); the variant uses // AMDGPUSubArch8_88A and records "gfx888" as its base name. -// CHECK: {[[#]], Triple::AMDGPUSubArch888, {{.*}}, {8, 8, 8}, [[FAM:[0-9]+]], 0, [[#]]}, -// CHECK: {[[#]], Triple::AMDGPUSubArch8_88A, {{.*}}, {8, 8, 8}, [[FAM]], [[#]], [[#]]}, +// CHECK: {[[#]], Triple::AMDGPUSubArch888, {{.*}}, {8, 8, 8}, [[FAM:[0-9]+]], 0, [[#]], [[#]]}, +// CHECK: {[[#]], Triple::AMDGPUSubArch8_88A, {{.*}}, {8, 8, 8}, [[FAM]], [[#]], [[#]], [[#]]}, // The subarch-name table maps the variant's own subarch to its triple name. // CHECK: {Triple::AMDGPUSubArch8_88A, [[#]], [[#]]}, diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index cd91aefb85b11..367df7a7b16df 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -3036,6 +3036,38 @@ TEST(TargetParserTest, testAMDGPUgetSGPRAllocGranule) { EXPECT_EQ(AMDGPU::getSGPRAllocGranule(AMDGPU::GK_GFX1030), 106u); } +TEST(TargetParserTest, testAMDGPUgetMaxHWAddressableLocalMemorySize) { + // The addressable cap is a fixed hardware property, independent of how many + // SIMDs a work-group runs on. + EXPECT_EQ( + AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::AMDGPUSubArch600), + 32768u); + EXPECT_EQ( + AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::AMDGPUSubArch700), + 65536u); + EXPECT_EQ( + AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::AMDGPUSubArch900), + 65536u); + EXPECT_EQ( + AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::AMDGPUSubArch950), + 163840u); + // gfx10+ addresses 64 KiB even though the physical block is 128 KiB. + EXPECT_EQ( + AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::AMDGPUSubArch1030), + 65536u); + EXPECT_EQ( + AMDGPU::getMaxHWAddressableLocalMemorySize(Triple::AMDGPUSubArch1250), + 327680u); + + // The GPUKind overload resolves to the same values. + EXPECT_EQ(AMDGPU::getMaxHWAddressableLocalMemorySize(AMDGPU::GK_GFX900), + 65536u); + EXPECT_EQ(AMDGPU::getMaxHWAddressableLocalMemorySize(AMDGPU::GK_GFX950), + 163840u); + EXPECT_EQ(AMDGPU::getMaxHWAddressableLocalMemorySize(AMDGPU::GK_GFX1250), + 327680u); +} + TEST(TargetParserTest, testAMDGPUgetNumWorkGroupSIMDs) { EXPECT_EQ(AMDGPU::getNumWorkGroupSIMDs(true), 4u); EXPECT_EQ(AMDGPU::getNumWorkGroupSIMDs(false), 2u); diff --git a/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp b/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp index bbbaf0db77022..9f4009a83cbc0 100644 --- a/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp @@ -598,7 +598,8 @@ emitAMDGPUTable(raw_ostream &OS, const RecordKeeper &RK, raw_svector_ostream BaseNameOS(BaseName); emitBaseName(BaseNameOS, R); OS << Names.GetOrAddStringOffset(BaseName) << ", " - << getFeatureValue(R, "MaxWavesPerEU", 10) << "},\n"; + << getFeatureValue(R, "MaxWavesPerEU", 10) << ", " + << getFeatureValue(R, "AddressableLocalMemorySize", 32768) << "},\n"; } OS << "};\n" "#endif // GET_AMDGPU_GPU_TABLE\n\n"; >From bdc08182cf41c9c9c2e03d38a6aba0d034219edd Mon Sep 17 00:00:00 2001 From: Chinmay Deshpande <[email protected]> Date: Wed, 26 Aug 2026 15:55:04 -0400 Subject: [PATCH 2/2] move back to using featurebits Change-Id: I4a86e755c01373b507fd5f8dc5dd1ad8a06e9ac8 --- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 4f4a5ff2f246b..a0648da67c06d 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1179,8 +1179,17 @@ unsigned getWavefrontSize(const MCSubtargetInfo &STI) { // Maximum LDS a single work-group can address. This is a fixed HW cap. It does // not depend on how many SIMDs a work-group runs on. static unsigned getMaxHWAddressableLocalMemorySize(const MCSubtargetInfo &STI) { - return AMDGPU::getMaxHWAddressableLocalMemorySize( - parseArchAMDGCN(STI.getCPU())); + if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize32768)) + return 32768; + if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize65536)) + return 65536; + if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize163840)) + return 163840; + if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize196608)) + return 196608; + if (STI.getFeatureBits().test(FeatureAddressableLocalMemorySize327680)) + return 327680; + return 32768; } // Total physical size of LDS on the block, in bytes. On targets with _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
