[llvm-branch-commits] [llvm] [AMDGPU] Verify VGPR tuple alignment from the operand register class (PR #219230)

[Valery Pykhtin via llvm-branch-commits]

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@@ -3016,6 +3016,93 @@ unsigned getRegBitWidth(const MCRegisterClass &RC) {
   return getRegBitWidth(RC.getID());
 }
 
+int getUnalignedEquivalentRC(unsigned RCID) {
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vpykhtin wrote:

Potentially yes, do you think it worth adding to this PR?

https://github.com/llvm/llvm-project/pull/219230
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