Author: Matt Arsenault Date: 2026-08-31T21:25:59+02:00 New Revision: 2359bcef25ca4fc140fc76fcfd928a80bc6d293f
URL: https://github.com/llvm/llvm-project/commit/2359bcef25ca4fc140fc76fcfd928a80bc6d293f DIFF: https://github.com/llvm/llvm-project/commit/2359bcef25ca4fc140fc76fcfd928a80bc6d293f.diff LOG: Hexagon: Fix early if-conversion crash on an undef PHI operand (#216815) Found by AI while working on something else. Co-authored-by: Claude (Opus 4.8) <[email protected]> Added: llvm/test/CodeGen/Hexagon/early-if-phi-undef.mir Modified: llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 2aca7e5bf6db3..ac3ab8543655c 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -399,9 +399,7 @@ bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const { if (!R.isVirtual()) continue; const MachineInstr *DefI = MRI->getVRegDef(R); - // "Undefined" virtual registers are actually defined via IMPLICIT_DEF. - assert(DefI && "Expecting a reaching def in MRI"); - if (DefI->isImplicitDef()) + if (!DefI || DefI->isImplicitDef()) return true; } return false; diff --git a/llvm/test/CodeGen/Hexagon/early-if-phi-undef.mir b/llvm/test/CodeGen/Hexagon/early-if-phi-undef.mir new file mode 100644 index 0000000000000..65be690675d67 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/early-if-phi-undef.mir @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=hexagon -run-pass=hexagon-early-if -o - %s | FileCheck %s + +# An undef PHI incoming value has no reaching def and must not be +# assert while checking whether the flow pattern is convertible. + +--- +name: undef_phi_operand +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: undef_phi_operand + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:intregs = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:intregs = COPY $r1 + ; CHECK-NEXT: [[C2_cmpeq:%[0-9]+]]:predregs = C2_cmpeq [[COPY]], [[COPY1]] + ; CHECK-NEXT: J2_jumpf [[C2_cmpeq]], %bb.2, implicit-def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[A2_addi:%[0-9]+]]:intregs = A2_addi [[COPY]], 1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:intregs = PHI [[COPY]], %bb.0, undef %5:intregs, %bb.1 + ; CHECK-NEXT: $r0 = COPY [[PHI]] + ; CHECK-NEXT: J2_jumpr $r31, implicit $r0, implicit-def $pc + bb.0: + liveins: $r0, $r1 + %0:intregs = COPY $r0 + %1:intregs = COPY $r1 + %3:predregs = C2_cmpeq %0, %1 + J2_jumpf %3, %bb.2, implicit-def $pc + + bb.1: + %4:intregs = A2_addi %0, 1 + + bb.2: + %6:intregs = PHI %0, %bb.0, undef %5:intregs, %bb.1 + $r0 = COPY %6 + J2_jumpr $r31, implicit $r0, implicit-def $pc +... _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
