Author: lrzlin Date: 2026-09-02T11:13:27+02:00 New Revision: 8e1810950d0ab2c266e574c0b80177e247204d5e
URL: https://github.com/llvm/llvm-project/commit/8e1810950d0ab2c266e574c0b80177e247204d5e DIFF: https://github.com/llvm/llvm-project/commit/8e1810950d0ab2c266e574c0b80177e247204d5e.diff LOG: [LoongArch] Add omitted LASX patterns for vector extend (#219351) Adds omitted 128-bit to 256-bit patterns for `sign_extend_vector_inreg`, including `v16i8 -> v4i64` and `v8i16 -> v4i64`, which will generate by the combination of `icmp + or/and/xor + zext/sext`, all related tests are added. Fix: https://github.com/llvm/llvm-project/issues/219224 (cherry picked from commit 715901096defbb408d9fb1a6f7e1959938d950c8) Added: llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll llvm/test/CodeGen/LoongArch/lasx/vec-zext-invec.ll Modified: llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td Removed: ################################################################################ diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index a1d1e96fca790..449457425d936 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -2333,15 +2333,21 @@ def : Pat<(v4i32 (sext_invec v16i8:$vj)), def : Pat<(v4i32 (sext_invec v8i16:$vj)), (v4i32 (EXTRACT_SUBREG (VEXT2XV_W_H (SUBREG_TO_REG v8i16:$vj, sub_128)), sub_128))>; -def : Pat<(v4i64 (sext_invec v32i8:$xj)), (v4i64 (VEXT2XV_D_B v32i8:$xj))>; -def : Pat<(v4i64 (sext_invec v16i16:$xj)), (v4i64 (VEXT2XV_D_H v16i16:$xj))>; -def : Pat<(v4i64 (sext_invec v8i32:$xj)), (v4i64 (VEXT2XV_D_W v8i32:$xj))>; def : Pat<(v8i16 (sext_invec v16i8:$vj)), (v8i16 (EXTRACT_SUBREG (VEXT2XV_H_B (SUBREG_TO_REG v16i8:$vj, sub_128)), sub_128))>; -def : Pat<(v16i16 (sext_invec v32i8:$xj)), (v16i16 (VEXT2XV_H_B v32i8:$xj))>; + +def : Pat<(v4i64 (sext_invec v32i8:$xj)), (v4i64 (VEXT2XV_D_B v32i8:$xj))>; +def : Pat<(v4i64 (sext_invec v16i16:$xj)), (v4i64 (VEXT2XV_D_H v16i16:$xj))>; +def : Pat<(v4i64 (sext_invec v8i32:$xj)), (v4i64 (VEXT2XV_D_W v8i32:$xj))>; def : Pat<(v8i32 (sext_invec v32i8:$xj)), (v8i32 (VEXT2XV_W_B v32i8:$xj))>; def : Pat<(v8i32 (sext_invec v16i16:$xj)), (v8i32 (VEXT2XV_W_H v16i16:$xj))>; +def : Pat<(v16i16 (sext_invec v32i8:$xj)), (v16i16 (VEXT2XV_H_B v32i8:$xj))>; + +def : Pat<(v4i64 (sext_invec v16i8:$vj)), + (v4i64 (VEXT2XV_D_B (SUBREG_TO_REG v16i8:$vj, sub_128)))>; +def : Pat<(v4i64 (sext_invec v8i16:$vj)), + (v4i64 (VEXT2XV_D_H (SUBREG_TO_REG v8i16:$vj, sub_128)))>; def : Pat<(v8i32 (sext_invec v16i8:$vj)), (v8i32 (VEXT2XV_W_B (SUBREG_TO_REG v16i8:$vj, sub_128)))>; @@ -2368,15 +2374,21 @@ def : Pat<(v4i32 (zext_invec v16i8:$vj)), def : Pat<(v4i32 (zext_invec v8i16:$vj)), (v4i32 (EXTRACT_SUBREG (VEXT2XV_WU_HU (SUBREG_TO_REG v8i16:$vj, sub_128)), sub_128))>; -def : Pat<(v4i64 (zext_invec v32i8:$xj)), (v4i64 (VEXT2XV_DU_BU v32i8:$xj))>; -def : Pat<(v4i64 (zext_invec v16i16:$xj)), (v4i64 (VEXT2XV_DU_HU v16i16:$xj))>; -def : Pat<(v4i64 (zext_invec v8i32:$xj)), (v4i64 (VEXT2XV_DU_WU v8i32:$xj))>; def : Pat<(v8i16 (zext_invec v16i8:$vj)), (v8i16 (EXTRACT_SUBREG (VEXT2XV_HU_BU (SUBREG_TO_REG v16i8:$vj, sub_128)), sub_128))>; -def : Pat<(v16i16 (zext_invec v32i8:$xj)), (v16i16 (VEXT2XV_HU_BU v32i8:$xj))>; + +def : Pat<(v4i64 (zext_invec v32i8:$xj)), (v4i64 (VEXT2XV_DU_BU v32i8:$xj))>; +def : Pat<(v4i64 (zext_invec v16i16:$xj)), (v4i64 (VEXT2XV_DU_HU v16i16:$xj))>; +def : Pat<(v4i64 (zext_invec v8i32:$xj)), (v4i64 (VEXT2XV_DU_WU v8i32:$xj))>; def : Pat<(v8i32 (zext_invec v32i8:$xj)), (v8i32 (VEXT2XV_WU_BU v32i8:$xj))>; def : Pat<(v8i32 (zext_invec v16i16:$xj)), (v8i32 (VEXT2XV_WU_HU v16i16:$xj))>; +def : Pat<(v16i16 (zext_invec v32i8:$xj)), (v16i16 (VEXT2XV_HU_BU v32i8:$xj))>; + +def : Pat<(v4i64 (zext_invec v16i8:$vj)), + (v4i64 (VEXT2XV_DU_BU (SUBREG_TO_REG v16i8:$vj, sub_128)))>; +def : Pat<(v4i64 (zext_invec v8i16:$vj)), + (v4i64 (VEXT2XV_DU_HU (SUBREG_TO_REG v8i16:$vj, sub_128)))>; def : Pat<(v8i32 (zext_invec v16i8:$vj)), (v8i32 (VEXT2XV_WU_BU (SUBREG_TO_REG v16i8:$vj, sub_128)))>; diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll new file mode 100644 index 0000000000000..4536027edc3aa --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll @@ -0,0 +1,251 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 + +;; This test covers 128-bit sign_extend_vector_inreg to 256-bit, which could +;; generated by the combination of setcc + logic operand (or/and/xor) pattern. +;; +;; Fix https://github.com/llvm/llvm-project/issues/219224 + +define void @zext_or_masks_v4i8_to_v4i64(ptr %ptr, ptr %dst) { +; CHECK-LABEL: zext_or_masks_v4i8_to_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 +; CHECK-NEXT: vrepli.b $vr1, 1 +; CHECK-NEXT: vslt.b $vr1, $vr1, $vr0 +; CHECK-NEXT: vseqi.b $vr0, $vr0, 0 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vext2xv.d.b $xr0, $xr0 +; CHECK-NEXT: xvrepli.d $xr1, 1 +; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %wide.load = load <4 x i8>, ptr %ptr + %A = icmp sgt <4 x i8> %wide.load, splat (i8 1) + %B = icmp eq <4 x i8> %wide.load, zeroinitializer + %C = or <4 x i1> %A, %B + %D = zext <4 x i1> %C to <4 x i64> + store <4 x i64> %D, ptr %dst + ret void +} + +define void @zext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) { +; LA32-LABEL: zext_or_masks_v4i16_to_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.h $vr1, 1 +; LA32-NEXT: vslt.h $vr1, $vr1, $vr0 +; LA32-NEXT: vseqi.h $vr0, $vr0, 0 +; LA32-NEXT: vor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vext2xv.d.h $xr0, $xr0 +; LA32-NEXT: xvrepli.d $xr1, 1 +; LA32-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA32-NEXT: xvst $xr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: zext_or_masks_v4i16_to_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.h $vr1, 1 +; LA64-NEXT: vslt.h $vr1, $vr1, $vr0 +; LA64-NEXT: vseqi.h $vr0, $vr0, 0 +; LA64-NEXT: vor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vext2xv.d.h $xr0, $xr0 +; LA64-NEXT: xvrepli.d $xr1, 1 +; LA64-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA64-NEXT: xvst $xr0, $a1, 0 +; LA64-NEXT: ret + %wide.load = load <4 x i16>, ptr %ptr + %A = icmp sgt <4 x i16> %wide.load, splat (i16 1) + %B = icmp eq <4 x i16> %wide.load, zeroinitializer + %C = or <4 x i1> %A, %B + %D = zext <4 x i1> %C to <4 x i64> + store <4 x i64> %D, ptr %dst + ret void +} + +define void @zext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) { +; LA32-LABEL: zext_or_masks_v8i8_to_v8i32: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.b $vr1, 1 +; LA32-NEXT: vslt.b $vr1, $vr1, $vr0 +; LA32-NEXT: vseqi.b $vr0, $vr0, 0 +; LA32-NEXT: vor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vext2xv.w.b $xr0, $xr0 +; LA32-NEXT: xvrepli.w $xr1, 1 +; LA32-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA32-NEXT: xvst $xr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: zext_or_masks_v8i8_to_v8i32: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 1 +; LA64-NEXT: vslt.b $vr1, $vr1, $vr0 +; LA64-NEXT: vseqi.b $vr0, $vr0, 0 +; LA64-NEXT: vor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vext2xv.w.b $xr0, $xr0 +; LA64-NEXT: xvrepli.w $xr1, 1 +; LA64-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA64-NEXT: xvst $xr0, $a1, 0 +; LA64-NEXT: ret + %wide.load = load <8 x i8>, ptr %ptr + %A = icmp sgt <8 x i8> %wide.load, splat (i8 1) + %B = icmp eq <8 x i8> %wide.load, zeroinitializer + %C = or <8 x i1> %A, %B + %D = zext <8 x i1> %C to <8 x i32> + store <8 x i32> %D, ptr %dst + ret void +} + +define void @sext_or_masks_v4i8_to_v4i64(ptr %ptr, ptr %dst) { +; CHECK-LABEL: sext_or_masks_v4i8_to_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 +; CHECK-NEXT: vrepli.b $vr1, 1 +; CHECK-NEXT: vslt.b $vr1, $vr1, $vr0 +; CHECK-NEXT: vseqi.b $vr0, $vr0, 0 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vext2xv.d.b $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %wide.load = load <4 x i8>, ptr %ptr + %A = icmp sgt <4 x i8> %wide.load, splat (i8 1) + %B = icmp eq <4 x i8> %wide.load, zeroinitializer + %C = or <4 x i1> %A, %B + %D = sext <4 x i1> %C to <4 x i64> + store <4 x i64> %D, ptr %dst + ret void +} + +define void @sext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) { +; LA32-LABEL: sext_or_masks_v4i16_to_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.h $vr1, 1 +; LA32-NEXT: vslt.h $vr1, $vr1, $vr0 +; LA32-NEXT: vseqi.h $vr0, $vr0, 0 +; LA32-NEXT: vor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vext2xv.d.h $xr0, $xr0 +; LA32-NEXT: xvst $xr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: sext_or_masks_v4i16_to_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.h $vr1, 1 +; LA64-NEXT: vslt.h $vr1, $vr1, $vr0 +; LA64-NEXT: vseqi.h $vr0, $vr0, 0 +; LA64-NEXT: vor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vext2xv.d.h $xr0, $xr0 +; LA64-NEXT: xvst $xr0, $a1, 0 +; LA64-NEXT: ret + %wide.load = load <4 x i16>, ptr %ptr + %A = icmp sgt <4 x i16> %wide.load, splat (i16 1) + %B = icmp eq <4 x i16> %wide.load, zeroinitializer + %C = or <4 x i1> %A, %B + %D = sext <4 x i1> %C to <4 x i64> + store <4 x i64> %D, ptr %dst + ret void +} + +define void @sext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) { +; LA32-LABEL: sext_or_masks_v8i8_to_v8i32: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.b $vr1, 1 +; LA32-NEXT: vslt.b $vr1, $vr1, $vr0 +; LA32-NEXT: vseqi.b $vr0, $vr0, 0 +; LA32-NEXT: vor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vext2xv.w.b $xr0, $xr0 +; LA32-NEXT: xvst $xr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: sext_or_masks_v8i8_to_v8i32: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 1 +; LA64-NEXT: vslt.b $vr1, $vr1, $vr0 +; LA64-NEXT: vseqi.b $vr0, $vr0, 0 +; LA64-NEXT: vor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vext2xv.w.b $xr0, $xr0 +; LA64-NEXT: xvst $xr0, $a1, 0 +; LA64-NEXT: ret + %wide.load = load <8 x i8>, ptr %ptr + %A = icmp sgt <8 x i8> %wide.load, splat (i8 1) + %B = icmp eq <8 x i8> %wide.load, zeroinitializer + %C = or <8 x i1> %A, %B + %D = sext <8 x i1> %C to <8 x i32> + store <8 x i32> %D, ptr %dst + ret void +} + +;; PromoteMaskArithmetic LHSTrunc/isExtVecInRegOpcode deal with LHS/RHS diff erently. + +define void @mixed_masks_wide_lhs(ptr %ptr, ptr %dst) { +; CHECK-LABEL: mixed_masks_wide_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a2, $a0, 0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a2, 0 +; CHECK-NEXT: xvrepli.d $xr2, 1 +; CHECK-NEXT: xvslt.d $xr0, $xr2, $xr0 +; CHECK-NEXT: vseqi.b $vr1, $vr1, 0 +; CHECK-NEXT: vext2xv.d.b $xr1, $xr1 +; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %x = load <4 x i64>, ptr %ptr + %y = load <4 x i8>, ptr %ptr + %A = icmp sgt <4 x i64> %x, splat (i64 1) + %B = icmp eq <4 x i8> %y, zeroinitializer + %C = or <4 x i1> %A, %B + %D = sext <4 x i1> %C to <4 x i64> + store <4 x i64> %D, ptr %dst + ret void +} + +define void @mixed_masks_wide_rhs(ptr %ptr, ptr %dst) { +; CHECK-LABEL: mixed_masks_wide_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a2, $a0, 0 +; CHECK-NEXT: xvld $xr0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a2, 0 +; CHECK-NEXT: xvrepli.d $xr2, 1 +; CHECK-NEXT: xvslt.d $xr0, $xr2, $xr0 +; CHECK-NEXT: xvpickev.w $xr0, $xr0, $xr0 +; CHECK-NEXT: xvpermi.d $xr0, $xr0, 216 +; CHECK-NEXT: vseqi.b $vr1, $vr1, 0 +; CHECK-NEXT: vext2xv.w.b $xr1, $xr1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vext2xv.d.w $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %x = load <4 x i64>, ptr %ptr + %y = load <4 x i8>, ptr %ptr + %A = icmp sgt <4 x i64> %x, splat (i64 1) + %B = icmp eq <4 x i8> %y, zeroinitializer + %C = or <4 x i1> %B, %A + %D = sext <4 x i1> %C to <4 x i64> + store <4 x i64> %D, ptr %dst + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-zext-invec.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-zext-invec.ll new file mode 100644 index 0000000000000..44210781c881b --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-zext-invec.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+lasx < %s | FileCheck %s + +;; This test covers 128-bit zero_extend_vector_inreg to 256-bit. +;; +;; Fix https://github.com/llvm/llvm-project/issues/219224 + +define void @zext_invec_v16i8_to_v4i64(ptr %ptr, ptr %dst) { +; CHECK-LABEL: zext_invec_v16i8_to_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vext2xv.du.bu $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %a = load <16 x i8>, ptr %ptr + %s = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, + <16 x i32> <i32 0, i32 16, i32 16, i32 16, i32 1, i32 16, i32 16, i32 16, + i32 2, i32 16, i32 16, i32 16, i32 3, i32 16, i32 16, i32 16> + %b = bitcast <16 x i8> %s to <4 x i32> + %r = zext <4 x i32> %b to <4 x i64> + store <4 x i64> %r, ptr %dst + ret void +} + +define void @zext_invec_v8i16_to_v4i64(ptr %ptr, ptr %dst) { +; CHECK-LABEL: zext_invec_v8i16_to_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vext2xv.du.hu $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %a = load <8 x i16>, ptr %ptr + %s = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, + <8 x i32> <i32 0, i32 8, i32 1, i32 8, i32 2, i32 8, i32 3, i32 8> + %b = bitcast <8 x i16> %s to <4 x i32> + %r = zext <4 x i32> %b to <4 x i64> + store <4 x i64> %r, ptr %dst + ret void +} + +define void @zext_invec_v16i8_to_v8i32(ptr %ptr, ptr %dst) { +; CHECK-LABEL: zext_invec_v16i8_to_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a0, 0 +; CHECK-NEXT: vext2xv.wu.bu $xr0, $xr0 +; CHECK-NEXT: xvst $xr0, $a1, 0 +; CHECK-NEXT: ret + %a = load <16 x i8>, ptr %ptr + %s = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, + <16 x i32> <i32 0, i32 16, i32 1, i32 16, i32 2, i32 16, i32 3, i32 16, + i32 4, i32 16, i32 5, i32 16, i32 6, i32 16, i32 7, i32 16> + %b = bitcast <16 x i8> %s to <8 x i16> + %r = zext <8 x i16> %b to <8 x i32> + store <8 x i32> %r, ptr %dst + ret void +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
