llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Domenic Nutile (saxlungs) <details> <summary>Changes</summary> DPP is not implemented for VGPR16 operands, so it should be disabled to allow verifying opcodes that would use the still work --- <sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub> --- Full diff: https://github.com/llvm/llvm-project/pull/222217.diff 1 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll (+61-70) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll b/llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll index 2ce1b3c55e9ae..29f0c92b4f6bd 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll @@ -3,14 +3,17 @@ ; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -mtriple=amdgpu10.30 < %s | FileCheck -check-prefix=GFX1030 %s -; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -check-prefix=GFX11 %s -; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX11 %s +; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s ; End to end coverage for the opcodes whose operands the sequencer reverses at ; runtime, so that DPP is applied to src1 instead of src0. Folding a DPP mov ; into src0 of one of those, either directly or by commuting a use into one, has ; to be rejected. +; Disable True16 for these tests, as DPP is currently not implemented for VGPR16 +; operands, so enabling it will mask targeted opcodes. + ; The DPP value is src1 of the subtract, so folding it would require commuting ; into v_subrev_u32/v_sub_nc_u32's REV form. Must stay a separate v_mov_b32_dpp. ; On gfx8 the subtract carries, so this is v_subrev_u32's carry out form. @@ -276,28 +279,32 @@ define amdgpu_kernel void @dpp_sub_u16_rev(ptr addrspace(1) %arg, i16 %in) { ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX11-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX11-NEXT: global_load_u16 v1, v0, s[0:1] +; GFX11-NEXT: v_mov_b32_e32 v2, s2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX11-NEXT: v_sub_nc_u16 v0.l, v0.l, v2.l -; GFX11-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_sub_nc_u16 v1, v1, v2 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: dpp_sub_u16_rev: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX12-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX12-NEXT: global_load_u16 v1, v0, s[0:1] +; GFX12-NEXT: v_mov_b32_e32 v2, s2 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX12-NEXT: v_sub_nc_u16 v0.l, v0.l, v2.l -; GFX12-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX12-NEXT: v_mov_b32_dpp v2, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_sub_nc_u16 v1, v1, v2 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %id = tail call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds i16, ptr addrspace(1) %arg, i32 %id @@ -561,32 +568,28 @@ define amdgpu_kernel void @dpp_fsub_f16(ptr addrspace(1) %arg, half %in) { ; ; GFX11-LABEL: dpp_fsub_f16: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX11-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX11-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX11-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l -; GFX11-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-NEXT: v_subrev_f16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: dpp_fsub_f16: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX12-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX12-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX12-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l -; GFX12-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX12-NEXT: v_subrev_f16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %id = tail call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds half, ptr addrspace(1) %arg, i32 %id @@ -963,32 +966,28 @@ define amdgpu_kernel void @dpp_shl_i16_amount(ptr addrspace(1) %arg, i16 %in) { ; ; GFX11-LABEL: dpp_shl_i16_amount: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX11-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX11-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX11-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l -; GFX11-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-NEXT: v_lshlrev_b16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: dpp_shl_i16_amount: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX12-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX12-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX12-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l -; GFX12-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX12-NEXT: v_lshlrev_b16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %id = tail call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds i16, ptr addrspace(1) %arg, i32 %id @@ -1066,32 +1065,28 @@ define amdgpu_kernel void @dpp_lshr_i16_amount(ptr addrspace(1) %arg, i16 %in) { ; ; GFX11-LABEL: dpp_lshr_i16_amount: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX11-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX11-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX11-NEXT: v_lshrrev_b16 v0.l, v2.l, v0.l -; GFX11-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-NEXT: v_lshrrev_b16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: dpp_lshr_i16_amount: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX12-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX12-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX12-NEXT: v_lshrrev_b16 v0.l, v2.l, v0.l -; GFX12-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX12-NEXT: v_lshrrev_b16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %id = tail call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds i16, ptr addrspace(1) %arg, i32 %id @@ -1169,32 +1164,28 @@ define amdgpu_kernel void @dpp_ashr_i16_amount(ptr addrspace(1) %arg, i16 %in) { ; ; GFX11-LABEL: dpp_ashr_i16_amount: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX11-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX11-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX11-NEXT: v_ashrrev_i16 v0.l, v2.l, v0.l -; GFX11-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-NEXT: v_ashrrev_i16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: dpp_ashr_i16_amount: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 1, v0 -; GFX12-NEXT: global_load_d16_b16 v0, v1, s[0:1] +; GFX12-NEXT: global_load_u16 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX12-NEXT: v_ashrrev_i16 v0.l, v2.l, v0.l -; GFX12-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX12-NEXT: v_ashrrev_i16_e64_dpp v1, v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %id = tail call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr inbounds i16, ptr addrspace(1) %arg, i32 %id `````````` </details> https://github.com/llvm/llvm-project/pull/222217 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
