llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-globalisel Author: llvmbot <details> <summary>Changes</summary> Backport 21970fad0f647e437bec90cd73b3092dac29e8d9 Requested by: @<!-- -->FlyGoat --- Full diff: https://github.com/llvm/llvm-project/pull/228891.diff 7 Files Affected: - (modified) llvm/lib/Target/Mips/MipsMSAInstrInfo.td (+2-4) - (modified) llvm/lib/Target/Mips/MipsScheduleGeneric.td (+1-1) - (modified) llvm/lib/Target/Mips/MipsScheduleI6400.td (+2-2) - (modified) llvm/lib/Target/Mips/MipsScheduleP5600.td (+1-1) - (modified) llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs_vec.ll (+2-2) - (modified) llvm/test/CodeGen/Mips/msa/arithmetic_float.ll (+2-2) - (modified) llvm/test/CodeGen/Mips/msa/buildvector-undef-loop.ll (+1-1) ``````````diff diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index 11c8c5b33a925..54e5d5c3eaa09 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -3465,11 +3465,9 @@ class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, [(set ROWD:$wd, (fabs ROWS:$ws))]>; def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, - PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, - MSA128WOpnd:$ws)>; + PseudoInstExpansion<(BCLRI_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 31)>; def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, - PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, - MSA128DOpnd:$ws)>; + PseudoInstExpansion<(BCLRI_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 63)>; class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td index d7b9a002dbc5f..9b9c479283ebb 100644 --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -1448,6 +1448,7 @@ def : InstRW<[GenericWriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^FABS_(W|D)$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; def : InstRW<[GenericWriteMSAShortInt], (instregex "^BMN*Z.*$")>; @@ -1507,7 +1508,6 @@ def : InstRW<[GenericWriteFPUS], (instregex "^FCULE_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FCULT_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FCUNE_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FCUN_(W|D)$")>; -def : InstRW<[GenericWriteFPUS], (instregex "^FABS_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FFQL_(W|D)$")>; def : InstRW<[GenericWriteFPUS], (instregex "^FFQR_(W|D)$")>; diff --git a/llvm/lib/Target/Mips/MipsScheduleI6400.td b/llvm/lib/Target/Mips/MipsScheduleI6400.td index 342e7ac31eb5a..ec2848dbe5373 100644 --- a/llvm/lib/Target/Mips/MipsScheduleI6400.td +++ b/llvm/lib/Target/Mips/MipsScheduleI6400.td @@ -246,7 +246,7 @@ let SchedModel = MipsI6400Model in { NLZC_B, NLZC_H, NLZC_W, NLZC_D, BNEG_B, BNEG_H, BNEG_W, BNEG_D, BNEGI_B, BNEGI_H, BNEGI_W, BNEGI_D, BCLR_B, BCLR_H, BCLR_W, BCLR_D, BCLRI_B, BCLRI_H, BCLRI_W, BCLRI_D, SHF_B, - SHF_H, SHF_W)>; + SHF_H, SHF_W, FABS_W, FABS_D)>; def I6400MSAShortLogic : SchedWriteRes<[I6400FPUShort]> { let ReleaseAtCycles = [2]; @@ -307,7 +307,7 @@ let SchedModel = MipsI6400Model in { } def : InstRW<[I6400MSAShortFloat], (instrs FMAX_W, FMAX_D, FMAX_A_W, FMAX_A_D, FMIN_W, FMIN_D, FMIN_A_W, FMIN_A_D, - FCLASS_W, FCLASS_D, FABS_D, FABS_W, + FCLASS_W, FCLASS_D, FABS_D32, FABS_D64)>; def I6400MSAFloatCompare : SchedWriteRes<[I6400FPUShort]> { let Latency = 2; diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td index e8b646a37932c..17ddb98be94c6 100644 --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -298,6 +298,7 @@ def : InstRW<[P5600WriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^FABS_(W|D)$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>; @@ -386,7 +387,6 @@ def : InstRW<[P5600WriteFPUS], (instregex "^FCULE_(W|D)$")>; def : InstRW<[P5600WriteFPUS], (instregex "^FCULT_(W|D)$")>; def : InstRW<[P5600WriteFPUS], (instregex "^FCUNE_(W|D)$")>; def : InstRW<[P5600WriteFPUS], (instregex "^FCUN_(W|D)$")>; -def : InstRW<[P5600WriteFPUS], (instregex "^FABS_(W|D)$")>; def : InstRW<[P5600WriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; def : InstRW<[P5600WriteFPUS], (instregex "^FFQL_(W|D)$")>; def : InstRW<[P5600WriteFPUS], (instregex "^FFQR_(W|D)$")>; diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs_vec.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs_vec.ll index 5a2715ce5dd09..15c534b734fb2 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs_vec.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs_vec.ll @@ -6,7 +6,7 @@ define void @fabs_v4f32(ptr %a, ptr %c) { ; P5600-LABEL: fabs_v4f32: ; P5600: # %bb.0: # %entry ; P5600-NEXT: ld.w $w0, 0($4) -; P5600-NEXT: fmax_a.w $w0, $w0, $w0 +; P5600-NEXT: bclri.w $w0, $w0, 31 ; P5600-NEXT: st.w $w0, 0($5) ; P5600-NEXT: jr $ra ; P5600-NEXT: nop @@ -22,7 +22,7 @@ define void @fabs_v2f64(ptr %a, ptr %c) { ; P5600-LABEL: fabs_v2f64: ; P5600: # %bb.0: # %entry ; P5600-NEXT: ld.d $w0, 0($4) -; P5600-NEXT: fmax_a.d $w0, $w0, $w0 +; P5600-NEXT: bclri.d $w0, $w0, 63 ; P5600-NEXT: st.d $w0, 0($5) ; P5600-NEXT: jr $ra ; P5600-NEXT: nop diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll index b97e0539fcf69..cf34550c32c63 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -217,7 +217,7 @@ define void @fabs_v4f32(ptr %c, ptr %a) nounwind { %1 = load <4 x float>, ptr %a ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) %2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1) - ; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]] + ; CHECK-DAG: bclri.w [[R3:\$w[0-9]+]], [[R1]], 31 store <4 x float> %2, ptr %c ; CHECK-DAG: st.w [[R3]], 0($4) @@ -231,7 +231,7 @@ define void @fabs_v2f64(ptr %c, ptr %a) nounwind { %1 = load <2 x double>, ptr %a ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) %2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1) - ; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]] + ; CHECK-DAG: bclri.d [[R3:\$w[0-9]+]], [[R1]], 63 store <2 x double> %2, ptr %c ; CHECK-DAG: st.d [[R3]], 0($4) diff --git a/llvm/test/CodeGen/Mips/msa/buildvector-undef-loop.ll b/llvm/test/CodeGen/Mips/msa/buildvector-undef-loop.ll index 80fa4049d0f10..8921bca8cc6e5 100644 --- a/llvm/test/CodeGen/Mips/msa/buildvector-undef-loop.ll +++ b/llvm/test/CodeGen/Mips/msa/buildvector-undef-loop.ll @@ -14,7 +14,7 @@ define void @nonsplatvalue_v4f32(float %a, float %b, float %c, float %d) nounwin ; MIPS64R5-NEXT: insve.w $w0[1], $w13[0] ; MIPS64R5-NEXT: insve.w $w0[2], $w14[0] ; MIPS64R5-NEXT: insve.w $w0[3], $w15[0] -; MIPS64R5-NEXT: fmax_a.w $w0, $w0, $w0 +; MIPS64R5-NEXT: bclri.w $w0, $w0, 31 ; MIPS64R5-NEXT: lui $1, %highest(v4f32) ; MIPS64R5-NEXT: daddiu $1, $1, %higher(v4f32) ; MIPS64R5-NEXT: dsll $1, $1, 16 `````````` </details> https://github.com/llvm/llvm-project/pull/228891 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
