llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-driver Author: Jonathan Thackray (jthackray) <details> <summary>Changes</summary> Add support for FEAT_LSC64B (single-copy atomic 64-byte load/store) instructions: - LDA64B - STL64B - STL64BV - STL64BV0 --- <sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub> --- Full diff: https://github.com/llvm/llvm-project/pull/229363.diff 12 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-aarch64.c (+1) - (modified) llvm/lib/Target/AArch64/AArch64Features.td (+3) - (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (+10-8) - (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+13-4) - (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+1) - (added) llvm/test/MC/AArch64/armv9.8a-lsc64b-diagnostics.s (+67) - (added) llvm/test/MC/AArch64/armv9.8a-lsc64b.s (+79) - (modified) llvm/test/MC/AArch64/directive-arch-negative.s (+6) - (modified) llvm/test/MC/AArch64/directive-arch.s (+4) - (modified) llvm/test/MC/AArch64/directive-arch_extension-negative.s (+6) - (modified) llvm/test/MC/AArch64/directive-arch_extension.s (+4) - (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+3-1) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c index a57fff693eec4..c35b1e080b21a 100644 --- a/clang/test/Driver/print-supported-extensions-aarch64.c +++ b/clang/test/Driver/print-supported-extensions-aarch64.c @@ -44,6 +44,7 @@ // CHECK-NEXT: ite FEAT_ITE Enable Armv9.4-A Instrumentation Extension // CHECK-NEXT: jscvt FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions // CHECK-NEXT: ls64 FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension +// CHECK-NEXT: lsc64b FEAT_LSC64B Enable Armv9.8-A Single-copy atomic 64-byte load/store consistency extension // CHECK-NEXT: lscp FEAT_LSCP Enable Armv9.7-A Load-acquire and store-release pair extension // CHECK-NEXT: lse FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions // CHECK-NEXT: lse128 FEAT_LSE128 Enable Armv9.4-A 128-bit Atomic instructions diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index fd1db78da1773..d70bdb44d34f5 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -624,6 +624,9 @@ def FeatureF16F32MM : ExtensionWithMArch<"f16f32mm", "F16F32MM", "FEAT_F16F32MM" def FeatureCFLT : ExtensionWithMArch<"cflt", "CFLT", "FEAT_CFLT", "Enable Armv9.8-A Conditional Fault instructions">; +def FeatureLSC64B : ExtensionWithMArch<"lsc64b", "LSC64B", "FEAT_LSC64B", + "Enable Armv9.8-A Single-copy atomic 64-byte load/store consistency extension", [FeatureLSCP]>; + //===----------------------------------------------------------------------===// // Future Architecture Technologies //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 7bdfd59f32834..754e4444cf0dc 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -12790,13 +12790,15 @@ multiclass STOPregisterLSUI<string asm, string instr> { !cast<Instruction>(instr # "X")>; } -class LoadStore64B_base<bits<3> opc, string asm_inst, string asm_ops, +class LoadStore64B_base<bits<2> ar, bits<3> opc, string asm_inst, string asm_ops, dag iops, dag oops, list<dag> pat> : I<oops, iops, asm_inst, asm_ops, "", pat>, Sched<[]> /* FIXME: fill in scheduling details once known */ { bits<5> Rt; bits<5> Rn; - let Inst{31-21} = 0b11111000001; + let Inst{31-24} = 0b11111000; + let Inst{23-22} = ar; + let Inst{21} = 1; let Inst{15} = 1; let Inst{14-12} = opc; let Inst{11-10} = 0b00; @@ -12806,24 +12808,24 @@ class LoadStore64B_base<bits<3> opc, string asm_inst, string asm_ops, let Predicates = [HasV8_7a]; } -class LoadStore64B<bits<3> opc, string asm_inst, dag iops, dag oops, +class LoadStore64B<bits<2> ar, bits<3> opc, string asm_inst, dag iops, dag oops, list<dag> pat = []> - : LoadStore64B_base<opc, asm_inst, "\t$Rt, [$Rn]", iops, oops, pat> { + : LoadStore64B_base<ar, opc, asm_inst, "\t$Rt, [$Rn]", iops, oops, pat> { let Inst{20-16} = 0b11111; } -multiclass LoadStore64B<bits<3> opc, string asm_inst, +multiclass LoadStore64B<bits<2> ar, bits<3> opc, string asm_inst, bit may_load, bit may_store, dag iops, dag oops, list<dag> pat = []> { let mayLoad = may_load, mayStore = may_store in - def "" : LoadStore64B<opc, asm_inst, iops, oops, pat>; + def "" : LoadStore64B<ar, opc, asm_inst, iops, oops, pat>; def : InstAlias<asm_inst # "\t$Rt, [$Rn, #0]", (!cast<Instruction>(NAME) GPR64x8:$Rt, GPR64sp:$Rn)>; } -class Store64BV<bits<3> opc, string asm_inst, list<dag> pat = []> - : LoadStore64B_base<opc, asm_inst, "\t$Rs, $Rt, [$Rn]", +class Store64BV<bits<2> ar, bits<3> opc, string asm_inst, list<dag> pat = []> + : LoadStore64B_base<ar, opc, asm_inst, "\t$Rs, $Rt, [$Rn]", (ins GPR64x8:$Rt, GPR64sp:$Rn), (outs GPR64:$Rs), pat> { bits<5> Rs; let Inst{20-16} = Rs; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 16131190410e8..8e64d275f9e35 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -239,6 +239,8 @@ def HasF16F32MM : Predicate<"Subtarget->hasF16F32MM()">, AssemblerPredicateWithAll<(all_of FeatureF16F32MM), "f16f32mm">; def HasCFLT : Predicate<"Subtarget->hasCFLT()">, AssemblerPredicateWithAll<(all_of FeatureCFLT), "cflt">; +def HasLSC64B : Predicate<"Subtarget->hasLSC64B()">, + AssemblerPredicateWithAll<(all_of FeatureLSC64B), "lsc64b">; // A subset of SVE(2) instructions are legal in Streaming SVE execution mode, // they should be enabled if either has been specified. @@ -12182,12 +12184,12 @@ foreach i = 0-7 in { } let Predicates = [HasLS64] in { - defm LD64B: LoadStore64B<0b101, "ld64b", 1, 0, (ins GPR64sp:$Rn), + defm LD64B: LoadStore64B<0b00, 0b101, "ld64b", 1, 0, (ins GPR64sp:$Rn), (outs GPR64x8:$Rt)>; - defm ST64B: LoadStore64B<0b001, "st64b", 0, 1, (ins GPR64x8:$Rt, GPR64sp:$Rn), + defm ST64B: LoadStore64B<0b00, 0b001, "st64b", 0, 1, (ins GPR64x8:$Rt, GPR64sp:$Rn), (outs)>; - def ST64BV: Store64BV<0b011, "st64bv">; - def ST64BV0: Store64BV<0b010, "st64bv0">; + def ST64BV: Store64BV<0b00, 0b011, "st64bv">; + def ST64BV0: Store64BV<0b00, 0b010, "st64bv0">; class ST64BPattern<Intrinsic intrinsic, Instruction instruction> : Pat<(intrinsic GPR64sp:$addr, GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3, GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7), @@ -12198,6 +12200,13 @@ let Predicates = [HasLS64] in { def : ST64BPattern<int_aarch64_st64bv0, ST64BV0>; } +let Predicates = [HasLSC64B] in { + defm LDA64B: LoadStore64B<0b10, 0b101, "lda64b", 1, 0, (ins GPR64sp:$Rn), (outs GPR64x8:$Rt)>; + defm STL64B: LoadStore64B<0b01, 0b001, "stl64b", 0, 1, (ins GPR64x8:$Rt, GPR64sp:$Rn), (outs)>; + def STL64BV: Store64BV<0b01, 0b011, "stl64bv">; + def STL64BV0: Store64BV<0b01, 0b010, "stl64bv0">; +} + let Predicates = [HasMOPS] in { let Defs = [NZCV] in { defm CPYFP : MOPSMemoryCopyInsns<0b00, "cpyfp">; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 626be6b020792..24800fe1f09b7 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3764,6 +3764,7 @@ constexpr EnumStringDef<FeatureBitset> ExtensionDefs[] = { {{"ssve-fexpa"}, {AArch64::FeatureSSVE_FEXPA}}, {{"wfxt"}, {AArch64::FeatureWFxT}}, {{"cflt"}, {AArch64::FeatureCFLT}}, + {{"lsc64b"}, {AArch64::FeatureLSC64B}}, }; constexpr auto ExtensionMap = BUILD_ENUM_STRINGS(ExtensionDefs); diff --git a/llvm/test/MC/AArch64/armv9.8a-lsc64b-diagnostics.s b/llvm/test/MC/AArch64/armv9.8a-lsc64b-diagnostics.s new file mode 100644 index 0000000000000..8f9c6035e4921 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.8a-lsc64b-diagnostics.s @@ -0,0 +1,67 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+lsc64b < %s 2>&1 \ +// RUN: | FileCheck %s + +lda64b w0, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: lda64b w0, [x13] +// CHECK-NEXT: ^ + +lda64b x23, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: lda64b x23, [x13] +// CHECK-NEXT: ^ + +lda64b x0, [x13, #8] +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: lda64b x0, [x13, #8] +// CHECK-NEXT: ^ + +stl64b w14, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: stl64b w14, [x13] +// CHECK-NEXT: ^ + +stl64b x29, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: stl64b x29, [x13] +// CHECK-NEXT: ^ + +stl64b x14, [x13, #8] +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: stl64b x14, [x13, #8] +// CHECK-NEXT: ^ + +stl64bv w1, x20, [x13] +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: stl64bv w1, x20, [x13] +// CHECK-NEXT: ^ + +stl64bv x1, w20, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: stl64bv x1, w20, [x13] +// CHECK-NEXT: ^ + +stl64bv x1, x23, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: stl64bv x1, x23, [x13] +// CHECK-NEXT: ^ + +stl64bv x1, x20, [x13, #0] +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: stl64bv x1, x20, [x13, #0] +// CHECK-NEXT: ^ + +stl64bv0 w1, x22, [x13] +// CHECK: error: invalid operand for instruction +// CHECK-NEXT: stl64bv0 w1, x22, [x13] +// CHECK-NEXT: ^ + +stl64bv0 x1, w22, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: stl64bv0 x1, w22, [x13] +// CHECK-NEXT: ^ + +stl64bv0 x1, x29, [x13] +// CHECK: error: expected an even-numbered x-register in the range [x0,x22] +// CHECK-NEXT: stl64bv0 x1, x29, [x13] +// CHECK-NEXT: ^ diff --git a/llvm/test/MC/AArch64/armv9.8a-lsc64b.s b/llvm/test/MC/AArch64/armv9.8a-lsc64b.s new file mode 100644 index 0000000000000..62a22d03cb291 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.8a-lsc64b.s @@ -0,0 +1,79 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsc64b < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsc64b < %s \ +// RUN: | llvm-objdump -d --mattr=+lsc64b --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsc64b < %s \ +// RUN: | llvm-objdump -d --mattr=-lsc64b --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsc64b < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+lsc64b -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +lda64b x0, [x13] +// CHECK-INST: lda64b x0, [x13] +// CHECK-ENCODING: encoding: [0xa0,0xd1,0xbf,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f8bfd1a0 <unknown> + +lda64b x2, [x13, #0] +// CHECK-INST: lda64b x2, [x13] +// CHECK-ENCODING: encoding: [0xa2,0xd1,0xbf,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f8bfd1a2 <unknown> + +lda64b x0, [sp] +// CHECK-INST: lda64b x0, [sp] +// CHECK-ENCODING: encoding: [0xe0,0xd3,0xbf,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f8bfd3e0 <unknown> + +lda64b x0, [sp, #0] +// CHECK-INST: lda64b x0, [sp] +// CHECK-ENCODING: encoding: [0xe0,0xd3,0xbf,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f8bfd3e0 <unknown> + +stl64b x14, [x13] +// CHECK-INST: stl64b x14, [x13] +// CHECK-ENCODING: encoding: [0xae,0x91,0x7f,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f87f91ae <unknown> + +stl64b x14, [sp, #0] +// CHECK-INST: stl64b x14, [sp] +// CHECK-ENCODING: encoding: [0xee,0x93,0x7f,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f87f93ee <unknown> + +stl64b x14, [x13, #0] +// CHECK-INST: stl64b x14, [x13] +// CHECK-ENCODING: encoding: [0xae,0x91,0x7f,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f87f91ae <unknown> + +stl64bv x1, x20, [x13] +// CHECK-INST: stl64bv x1, x20, [x13] +// CHECK-ENCODING: encoding: [0xb4,0xb1,0x61,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f861b1b4 <unknown> + +stl64bv x1, x20, [sp] +// CHECK-INST: stl64bv x1, x20, [sp] +// CHECK-ENCODING: encoding: [0xf4,0xb3,0x61,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f861b3f4 <unknown> + +stl64bv0 x1, x22, [x13] +// CHECK-INST: stl64bv0 x1, x22, [x13] +// CHECK-ENCODING: encoding: [0xb6,0xa1,0x61,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f861a1b6 <unknown> + +stl64bv0 x1, x22, [sp] +// CHECK-INST: stl64bv0 x1, x22, [sp] +// CHECK-ENCODING: encoding: [0xf6,0xa3,0x61,0xf8] +// CHECK-ERROR: error: instruction requires: lsc64b +// CHECK-UNKNOWN: f861a3f6 <unknown> diff --git a/llvm/test/MC/AArch64/directive-arch-negative.s b/llvm/test/MC/AArch64/directive-arch-negative.s index 2e7bed1ef2692..9228373c11623 100644 --- a/llvm/test/MC/AArch64/directive-arch-negative.s +++ b/llvm/test/MC/AArch64/directive-arch-negative.s @@ -85,3 +85,9 @@ # CHECK: error: instruction requires: cflt # CHECK-NEXT: cfltz #1, w0 + + .arch armv9-a+lsc64b+nolsc64b + lda64b x0, [x13] + +# CHECK: [[@LINE-2]]:9: error: instruction requires: lsc64b +# CHECK-NEXT: lda64b x0, [x13] diff --git a/llvm/test/MC/AArch64/directive-arch.s b/llvm/test/MC/AArch64/directive-arch.s index cd68b6651448f..bf58fb132f0eb 100644 --- a/llvm/test/MC/AArch64/directive-arch.s +++ b/llvm/test/MC/AArch64/directive-arch.s @@ -42,3 +42,7 @@ .arch armv9-a+cflt cfltz #1, w0 # CHECK: cflteq #1, w0, #0 + + .arch armv9-a+lsc64b + lda64b x0, [x13] +# CHECK: lda64b x0, [x13] diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s index 7d6f608ea47cd..c6d5ecebeff28 100644 --- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s +++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s @@ -256,3 +256,9 @@ fmmla v2.4s, v1.16b, v0.16b cfltz #1, w0 // CHECK: [[@LINE-1]]:1: error: instruction requires: cflt // CHECK-NEXT: cfltz #1, w0 + +.arch_extension lsc64b +.arch_extension nolsc64b +lda64b x0, [x13] +// CHECK: [[@LINE-1]]:1: error: instruction requires: lsc64b +// CHECK-NEXT: lda64b x0, [x13] diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s b/llvm/test/MC/AArch64/directive-arch_extension.s index 6f4274f0e0edf..bd6a3924e7470 100644 --- a/llvm/test/MC/AArch64/directive-arch_extension.s +++ b/llvm/test/MC/AArch64/directive-arch_extension.s @@ -88,6 +88,10 @@ stilp w24, w0, [x16, #-8]! ld64b x0, [x13] // CHECK: ld64b x0, [x13] +.arch_extension lsc64b +lda64b x0, [x13] +// CHECK: lda64b x0, [x13] + .arch_extension pauth paciasp // CHECK: paciasp diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 824cbaffe7833..6f2dfbc268b17 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1505,7 +1505,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { AArch64::AEK_BTIE, AArch64::AEK_F64MM, AArch64::AEK_POPS, AArch64::AEK_SVESM4, AArch64::AEK_MTETC, AArch64::AEK_HINTE, - AArch64::AEK_CFLT, + AArch64::AEK_CFLT, AArch64::AEK_LSC64B, }; std::vector<StringRef> Features; @@ -1631,6 +1631,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) { EXPECT_TRUE(llvm::is_contained(Features, "+btie")); EXPECT_TRUE(llvm::is_contained(Features, "+hinte")); EXPECT_TRUE(llvm::is_contained(Features, "+cflt")); + EXPECT_TRUE(llvm::is_contained(Features, "+lsc64b")); // Assuming we listed every extension above, this should produce the same // result. @@ -1813,6 +1814,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"btie", "nobtie", "+btie", "-btie"}, {"hinte", "nohinte", "+hinte", "-hinte"}, {"cflt", "nocflt", "+cflt", "-cflt"}, + {"lsc64b", "nolsc64b", "+lsc64b", "-lsc64b"}, }; for (unsigned i = 0; i < std::size(ArchExt); i++) { `````````` </details> https://github.com/llvm/llvm-project/pull/229363 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
