Author: Chinmay Deshpande Date: 2026-10-08T10:51:43-07:00 New Revision: 6fed68b7968b6d0a5c3fed57ce541fa0124962f8
URL: https://github.com/llvm/llvm-project/commit/6fed68b7968b6d0a5c3fed57ce541fa0124962f8 DIFF: https://github.com/llvm/llvm-project/commit/6fed68b7968b6d0a5c3fed57ce541fa0124962f8.diff LOG: Revert "[AMDGPU] Reserve ENABLE_WAVEFRONT_SIZE32 on gfx125x (#229162)" This reverts commit a2c07d5107f16c3e804c6599c49f5080303378ab. Added: Modified: llvm/docs/AMDGPUUsage.rst llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll llvm/test/MC/AMDGPU/hsa-diag-v4.s llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s llvm/test/MC/Disassembler/AMDGPU/kernel-descriptor-errors.test llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s Removed: ################################################################################ diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index c57a013ff889a..2d2db2990db96 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -6326,9 +6326,9 @@ The fields used by CP for code objects before V3 also match those specified in >454 1 bit ENABLE_SGPR_PRIVATE_SEGMENT _SIZE 457:455 3 bits Reserved, must be 0. - 458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-GFX9, GFX125* + 458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-GFX9 Reserved, must be 0. - GFX10-GFX11, GFX120*, GFX13 + GFX10-GFX11 - If 0 execute in wavefront size 64 mode. - If 1 execute in @@ -21868,9 +21868,9 @@ terminated by an ``.end_amdhsa_kernel`` directive. GFX942) ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX12 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_wavefront_size32`` Target GFX10-GFX13 Controls ENABLE_WAVEFRONT_SIZE32 in - Feature (except :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - Specific GFX125*) + ``.amdhsa_wavefront_size32`` Target GFX10-GFX12 Controls ENABLE_WAVEFRONT_SIZE32 in + Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. + Specific (wavefrontsize64) ``.amdhsa_uses_dynamic_stack`` 0 GFX6-GFX12 Controls USES_DYNAMIC_STACK in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 64c71c09201eb..06acc7613d660 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -832,10 +832,7 @@ const MCExpr *AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties( KernelCodeProperties |= amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE; } - const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); - if (STM.isWave32() && - STM.getFeatureBits().test(AMDGPU::FeatureSupportsWave32) && - STM.getFeatureBits().test(AMDGPU::FeatureSupportsWave64)) { + if (MF.getSubtarget<GCNSubtarget>().isWave32()) { KernelCodeProperties |= amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32; } diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index a505ff1aadbdb..2a37bccb4c5c6 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -6216,11 +6216,6 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { EXPR_RESOLVE_OR_ERROR(EvaluatableExpr); if (ISA.Major < 10) return Error(IDRange.Start, "directive requires gfx10+", IDRange); - if (!(getFeatureBits().test(AMDGPU::FeatureSupportsWave32) && - getFeatureBits().test(AMDGPU::FeatureSupportsWave64))) { - return Error(IDRange.Start, - "directive unsupported on " + getSTI().getCPU(), IDRange); - } EnableWavefrontSize32 = Val; PARSE_BITS_ENTRY(KD.kernel_code_properties, KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, ExprVal, diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index ed360054c7485..da039141fd2a3 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -2992,15 +2992,16 @@ Expected<bool> AMDGPUDisassembler::decodeKernelDescriptorDirective( return createReservedKDBitsError(KERNEL_CODE_PROPERTY_RESERVED0, amdhsa::KERNEL_CODE_PROPERTIES_OFFSET); - // Reserved unless both wave sizes are supported. - if (STI.getFeatureBits().test(AMDGPU::FeatureSupportsWave32) && - STI.getFeatureBits().test(AMDGPU::FeatureSupportsWave64)) { - PRINT_DIRECTIVE(".amdhsa_wavefront_size32", - KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); - } else if (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) { + // Reserved for GFX9 + if (isGFX9() && + (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { return createReservedKDBitsError( KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, - amdhsa::KERNEL_CODE_PROPERTIES_OFFSET); + amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, "must be zero on gfx9"); + } + if (isGFX10Plus()) { + PRINT_DIRECTIVE(".amdhsa_wavefront_size32", + KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); } if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) @@ -3057,8 +3058,7 @@ Expected<bool> AMDGPUDisassembler::decodeKernelDescriptor( // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong // order. Workaround this by first looking up .amdhsa_wavefront_size32 here // when required. - if (STI.getFeatureBits().test(AMDGPU::FeatureSupportsWave32) && - STI.getFeatureBits().test(AMDGPU::FeatureSupportsWave64)) { + if (isGFX10Plus()) { uint16_t KernelCodeProperties = support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], llvm::endianness::little); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp index 3d384de8a6c7d..6501905a67b4a 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp @@ -55,14 +55,11 @@ MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI, amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT, amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Ctx); if (Version.Major >= 10) { - if (STI->getFeatureBits().test(FeatureWavefrontSize32) && - STI->getFeatureBits().test(FeatureSupportsWave32) && - STI->getFeatureBits().test(FeatureSupportsWave64)) { + if (STI->getFeatureBits().test(FeatureWavefrontSize32)) MCKernelDescriptor::bits_set( KD.kernel_code_properties, OneMCExpr, amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT, amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, Ctx); - } if (!STI->getFeatureBits().test(FeatureCuMode)) MCKernelDescriptor::bits_set( KD.compute_pgm_rsrc1, OneMCExpr, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp index 230e7cb5472d3..0f8b59ac9fe26 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -390,13 +390,11 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT, amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE, ".amdhsa_user_sgpr_private_segment_size"); - if (STI.getFeatureBits().test(AMDGPU::FeatureSupportsWave32) && - STI.getFeatureBits().test(AMDGPU::FeatureSupportsWave64)) { + if (IVersion.Major >= 10) PrintField(KD.kernel_code_properties, amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT, amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, ".amdhsa_wavefront_size32"); - } if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) PrintField(KD.kernel_code_properties, amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT, diff --git a/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll b/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll index 6031412ac5736..f4876e53f46e0 100644 --- a/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll @@ -75,7 +75,7 @@ define amdgpu_kernel void @amdhsa_kernarg_preload_0_implicit_2(i32) #0 { ret voi ; GFX1250-OBJDUMP: 0100 00000000 00000000 90010000 00000000 ................ ; GFX1250-OBJDUMP: 0110 00000000 00000000 00000000 00000000 ................ ; GFX1250-OBJDUMP: 0120 00000000 00000000 00000000 10000000 ................ -; GFX1250-OBJDUMP: 0130 00000fc0 c0130000 1e001800 00000000 ................ +; GFX1250-OBJDUMP: 0130 00000fc0 c0130000 1e041800 00000000 ................ ; GFX1250-ASM: .sgpr_count: 66 define amdgpu_kernel void @many__i32( i32 inreg %a0, i32 inreg %a1, i32 inreg %a2, i32 inreg %a3, diff --git a/llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll b/llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll index 9a0f5698ab00e..4f49630b72771 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll @@ -19,7 +19,7 @@ ; RUN: llc --amdhsa-code-object-version=6 -mtriple=amdgpu11.7-amd-amdhsa -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=W64 %s ; RUN: llc --amdhsa-code-object-version=6 -mtriple=amdgpu12-amd-amdhsa -mattr=+wavefrontsize32 < %s | FileCheck -check-prefix=W32 %s ; RUN: llc --amdhsa-code-object-version=6 -mtriple=amdgpu12-amd-amdhsa -mattr=+wavefrontsize64 < %s | FileCheck -check-prefix=W64 %s -; RUN: llc --amdhsa-code-object-version=6 -mtriple=amdgpu12.5-amd-amdhsa < %s | FileCheck -check-prefix=W32ONLY %s +; RUN: llc --amdhsa-code-object-version=6 -mtriple=amdgpu12.5-amd-amdhsa < %s | FileCheck -check-prefix=W32 %s ; Checks 10.1, 10.3, 11, 11.7 and 12 generic targets allow cumode/wave64. @@ -31,10 +31,6 @@ ; W64: .amdhsa_wavefront_size32 0 ; W32: .amdhsa_wavefront_size32 1 -; W32ONLY: .amdhsa_kernel wavefrontsize -; W32ONLY-NOT: .amdhsa_wavefront_size32 -; W32ONLY: .end_amdhsa_kernel - define amdgpu_kernel void @wavefrontsize() { entry: ret void diff --git a/llvm/test/MC/AMDGPU/hsa-diag-v4.s b/llvm/test/MC/AMDGPU/hsa-diag-v4.s index 129834cd94b2c..6696f23169cd6 100644 --- a/llvm/test/MC/AMDGPU/hsa-diag-v4.s +++ b/llvm/test/MC/AMDGPU/hsa-diag-v4.s @@ -1,8 +1,8 @@ // RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu8.10-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s -DMCPU=gfx810 --check-prefixes=ALL,GCN,GFX8,PREGFX10,NOWGP,AMDHSA -// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu10.10-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=ALL,GCN,GFX10PLUS,GFX10PLUS-W64,GFX10,AMDHSA -// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu11.00-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=ALL,GCN,GFX10PLUS,GFX10PLUS-W64,GFX11,AMDHSA -// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu12.00-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s -DMCPU=gfx1200 --check-prefixes=ALL,GCN,GFX10PLUS,GFX10PLUS-W64,GFX12,AMDHSA -// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu11.70-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=ALL,GCN,GFX10PLUS,GFX10PLUS-W64,GFX1170,AMDHSA +// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu10.10-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=ALL,GCN,GFX10PLUS,GFX10,AMDHSA +// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu11.00-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=ALL,GCN,GFX10PLUS,GFX11,AMDHSA +// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu12.00-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s -DMCPU=gfx1200 --check-prefixes=ALL,GCN,GFX10PLUS,GFX12,AMDHSA +// RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu11.70-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=ALL,GCN,GFX10PLUS,GFX1170,AMDHSA // RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu8.10-amd- %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=ALL,GCN,NONAMDHSA // RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu9.0a-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s -DMCPU=gfx90a --check-prefixes=ALL,GFX90A,PREGFX10,NOWGP,AMDHSA // RUN: not llvm-mc --amdhsa-code-object-version=4 -triple=amdgpu12.50-amd-amdhsa %s -filetype=null 2>&1 | FileCheck %s -DMCPU=gfx1250 --check-prefixes=ALL,GCN,GFX10PLUS,GFX1250,NOWGP,AMDHSA @@ -163,8 +163,7 @@ // ALL-LABEL: warning: test_amdhsa_wavefront_size32 // PREGFX10: error: directive requires gfx10+ -// GFX10PLUS-W64: error: .amdhsa_next_free_vgpr directive is required -// GFX1250: error: directive unsupported on gfx1250 +// GFX10PLUS: error: .amdhsa_next_free_vgpr directive is required // NONAMDHSA: error: unknown directive .warning "test_amdhsa_wavefront_size32" .amdhsa_kernel test_amdhsa_wavefront_size32 @@ -173,8 +172,7 @@ // GCN-LABEL: warning: test_amdhsa_wavefront_size32_invalid // PREGFX10: error: directive requires gfx10+ -// GFX10PLUS-W64: error: value out of range -// GFX1250: error: directive unsupported on gfx1250 +// GFX10PLUS: error: value out of range // NONAMDHSA: error: unknown directive .warning "test_amdhsa_wavefront_size32_invalid" .amdhsa_kernel test_amdhsa_wavefront_size32_invalid diff --git a/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s b/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s index e36d851485875..7f80c9392db69 100644 --- a/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s +++ b/llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s @@ -35,32 +35,32 @@ // OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 0030 00000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 0030 00000cc0 80000000 00040000 00000000 // complete // OBJDUMP-NEXT: 0040 01000000 01000000 0c000000 00000000 // OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00c00000 -// OBJDUMP-NEXT: 0070 005021c4 410f007f 5e008200 00000000 +// OBJDUMP-NEXT: 0070 005021c4 410f007f 5e048200 00000000 // special_sgpr // OBJDUMP-NEXT: 0080 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 00b0 000000c0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 00b0 000000c0 80000000 00040000 00000000 // disabled_user_sgpr // OBJDUMP-NEXT: 00c0 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 00d0 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 00f0 00000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 00f0 00000cc0 80000000 00040000 00000000 // max_lds_size // OBJDUMP-NEXT: 0100 00000500 00000000 00000000 00000000 // OBJDUMP-NEXT: 0110 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0120 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 0130 00000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 0130 00000cc0 80000000 00040000 00000000 // max_vgprs // OBJDUMP-NEXT: 0140 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0150 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0160 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 0170 3f000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 0170 3f000cc0 80000000 00040000 00000000 .text @@ -145,6 +145,7 @@ max_vgprs: .amdhsa_user_sgpr_kernarg_preload_length 2 .amdhsa_user_sgpr_kernarg_preload_offset 1 .amdhsa_user_sgpr_private_segment_size 1 + .amdhsa_wavefront_size32 1 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 0 .amdhsa_system_sgpr_workgroup_id_y 1 @@ -184,6 +185,7 @@ max_vgprs: // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_length 2 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_offset 1 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 1 +// ASM-NEXT: .amdhsa_wavefront_size32 1 // ASM-NEXT: .amdhsa_enable_private_segment 1 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 0 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1 diff --git a/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s b/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s index 32ae2f1eee71f..ccab72b10a133 100644 --- a/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s +++ b/llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s @@ -35,32 +35,32 @@ // OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 0030 00000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 0030 00000cc0 80000000 00040000 00000000 // complete // OBJDUMP-NEXT: 0040 01000000 01000000 0c000000 00000000 // OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00c00000 -// OBJDUMP-NEXT: 0070 005021c4 410f007f 5e008200 00000000 +// OBJDUMP-NEXT: 0070 005021c4 410f007f 5e048200 00000000 // special_sgpr // OBJDUMP-NEXT: 0080 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 00b0 000000c0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 00b0 000000c0 80000000 00040000 00000000 // disabled_user_sgpr // OBJDUMP-NEXT: 00c0 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 00d0 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 00f0 00000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 00f0 00000cc0 80000000 00040000 00000000 // max_lds_size // OBJDUMP-NEXT: 0100 00000500 00000000 00000000 00000000 // OBJDUMP-NEXT: 0110 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0120 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 0130 00000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 0130 00000cc0 80000000 00040000 00000000 // max_vgprs // OBJDUMP-NEXT: 0140 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0150 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0160 00000000 00000000 00000000 00000000 -// OBJDUMP-NEXT: 0170 3f000cc0 80000000 00000000 00000000 +// OBJDUMP-NEXT: 0170 3f000cc0 80000000 00040000 00000000 .text @@ -145,6 +145,7 @@ max_vgprs: .amdhsa_user_sgpr_kernarg_preload_length 2 .amdhsa_user_sgpr_kernarg_preload_offset 1 .amdhsa_user_sgpr_private_segment_size 1 + .amdhsa_wavefront_size32 1 .amdhsa_enable_private_segment 1 .amdhsa_system_sgpr_workgroup_id_x 0 .amdhsa_system_sgpr_workgroup_id_y 1 @@ -184,6 +185,7 @@ max_vgprs: // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_length 2 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_offset 1 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 1 +// ASM-NEXT: .amdhsa_wavefront_size32 1 // ASM-NEXT: .amdhsa_enable_private_segment 1 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 0 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1 diff --git a/llvm/test/MC/Disassembler/AMDGPU/kernel-descriptor-errors.test b/llvm/test/MC/Disassembler/AMDGPU/kernel-descriptor-errors.test index df98012754404..fdca11b95caa6 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/kernel-descriptor-errors.test +++ b/llvm/test/MC/Disassembler/AMDGPU/kernel-descriptor-errors.test @@ -20,11 +20,7 @@ # RUN: yaml2obj %s -DGPU=GFX90A -DKD=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c000000000000 \ # RUN: | llvm-objdump --disassemble-symbols=test.kd - | FileCheck %s --check-prefix=WF32 -# RUN: yaml2obj %s -DGPU=GFX803 -DKD=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000 \ -# RUN: | llvm-objdump --disassemble-symbols=test.kd - | FileCheck %s --check-prefix=WF32 -# RUN: yaml2obj %s -DGPU=GFX1250 -DKD=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000 \ -# RUN: | llvm-objdump --disassemble-symbols=test.kd - | FileCheck %s --check-prefix=WF32 -# WF32: ; error decoding test.kd: kernel descriptor reserved bit (458) set{{$}} +# WF32: ; error decoding test.kd: kernel descriptor reserved bit (458) set, must be zero on gfx9 # WF32-NEXT: ; decoding failed region as bytes # RUN: yaml2obj %s -DGPU=GFX1100 -DKD=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300AC60800000000024000000000000 \ diff --git a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s index c0bdcb3929847..2a45c60ef8979 100644 --- a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s +++ b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s @@ -49,6 +49,7 @@ ; CHECK-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 ; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; CHECK-NEXT: .amdhsa_user_sgpr_private_segment_size 0 +; CHECK-NEXT: .amdhsa_wavefront_size32 1 ; CHECK-NEXT: .amdhsa_uses_dynamic_stack 0 ; CHECK-NEXT: .end_amdhsa_kernel .amdhsa_kernel kernel @@ -104,6 +105,7 @@ ; CHECK-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 ; CHECK-NEXT: .amdhsa_user_sgpr_dispatch_id 0 ; CHECK-NEXT: .amdhsa_user_sgpr_private_segment_size 0 +; CHECK-NEXT: .amdhsa_wavefront_size32 1 ; CHECK-NEXT: .amdhsa_uses_dynamic_stack 0 ; CHECK-NEXT: .end_amdhsa_kernel .amdhsa_kernel kernel _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
