Author: Luke Lau Date: 2026-10-09T13:14:12+01:00 New Revision: df0ee94bb85847ac345404e4a1872da888314f08
URL: https://github.com/llvm/llvm-project/commit/df0ee94bb85847ac345404e4a1872da888314f08 DIFF: https://github.com/llvm/llvm-project/commit/df0ee94bb85847ac345404e4a1872da888314f08.diff LOG: Revert "[DAG] Expand mask_beforefirst during promotion (#230163)" This reverts commit 001b1abc28a7f22345b8b326d0ec4aca88743292. Added: Modified: llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/test/CodeGen/AArch64/mask-beforefirst-sve.ll Removed: ################################################################################ diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index bb549118ec0b8..9762184ca825f 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -5897,11 +5897,6 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase { /// \returns The expansion result or SDValue() if it fails. SDValue expandLoopDependenceMask(SDNode *N, SelectionDAG &DAG) const; - /// Expand MASK_BEFOREFIRST nodes - /// \param N Node to expand - /// \returns The expansion result or SDValue() if it fails. - SDValue expandMaskBeforeFirst(SDNode *N, SelectionDAG &DAG) const; - /// Expand ABS nodes. Expands vector/scalar ABS nodes, /// vector nodes can only succeed if all operations are legal/custom. /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size)) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 51a9f2695483c..080cedce8a7df 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -6465,13 +6465,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_MASK_BEFOREFIRST(SDNode *N) { EVT VT = N->getValueType(0); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); - - // If the promoted MASK_BEFOREFIRST isn't supported by the target, try to - // expand now so the target can lower cttz_elts on the original mask type. - if (!TLI.isOperationLegalOrCustom(ISD::MASK_BEFOREFIRST, NVT)) - return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, - TLI.expandMaskBeforeFirst(N, DAG)); - SDValue Op = PromoteTargetBoolean(N->getOperand(0), NVT); return DAG.getNode(ISD::MASK_BEFOREFIRST, SDLoc(N), NVT, Op); } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index b170ce8adeac4..cee904bc151fa 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -1795,7 +1795,14 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) { } SDValue VectorLegalizer::ExpandMASK_BEFOREFIRST(SDNode *N) { - return TLI.expandMaskBeforeFirst(N, DAG); + // Expand to (get_active_lane_mask 0, (cttz_elts x)) + SDLoc DL(N); + EVT VT = N->getValueType(0); + EVT VecIdxVT = TLI.getVectorIdxTy(DAG.getDataLayout()); + SDValue CttzElts = + DAG.getNode(ISD::CTTZ_ELTS, DL, VecIdxVT, N->getOperand(0)); + return DAG.getNode(ISD::GET_ACTIVE_LANE_MASK, DL, VT, + DAG.getConstant(0, DL, VecIdxVT), CttzElts); } SDValue VectorLegalizer::ExpandMaskedBinOp(SDNode *N) { diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 8c10c9e35ff3c..151e6b1c14b9d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -11479,18 +11479,6 @@ SDValue TargetLowering::expandLoopDependenceMask(SDNode *N, return DAG.getNode(ISD::GET_ACTIVE_LANE_MASK, DL, VT, LaneOffset, MaskN); } -SDValue TargetLowering::expandMaskBeforeFirst(SDNode *N, - SelectionDAG &DAG) const { - // Expand to (get_active_lane_mask 0, (cttz_elts x)) - SDLoc DL(N); - EVT VT = N->getValueType(0); - EVT VecIdxVT = getVectorIdxTy(DAG.getDataLayout()); - SDValue CttzElts = - DAG.getNode(ISD::CTTZ_ELTS, DL, VecIdxVT, N->getOperand(0)); - return DAG.getNode(ISD::GET_ACTIVE_LANE_MASK, DL, VT, - DAG.getConstant(0, DL, VecIdxVT), CttzElts); -} - SDValue TargetLowering::expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative) const { SDLoc dl(N); diff --git a/llvm/test/CodeGen/AArch64/mask-beforefirst-sve.ll b/llvm/test/CodeGen/AArch64/mask-beforefirst-sve.ll index 9f9d9029ee8df..793a7a7303594 100644 --- a/llvm/test/CodeGen/AArch64/mask-beforefirst-sve.ll +++ b/llvm/test/CodeGen/AArch64/mask-beforefirst-sve.ll @@ -41,14 +41,22 @@ define <vscale x 2 x i1> @nxv2i1(<vscale x 2 x i1> %m) { ret <vscale x 2 x i1> %x } +; TODO: Use brkb for fixed length vectors. + define <16 x i1> @v16i1(<16 x i1> %m) { ; CHECK-LABEL: v16i1: ; CHECK: // %bb.0: ; CHECK-NEXT: shl v0.16b, v0.16b, #7 -; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, #0 -; CHECK-NEXT: brkb p1.b, p0/z, p1.b -; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: adrp x8, .LCPI4_0 +; CHECK-NEXT: mov w9, #16 // =0x10 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] +; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b +; CHECK-NEXT: umaxv b0, v0.16b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: sub w8, w9, w8, uxtb +; CHECK-NEXT: whilelo p0.b, xzr, x8 +; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret %x = call <16 x i1> @llvm.mask.beforefirst(<16 x i1> %m) @@ -59,10 +67,15 @@ define <8 x i1> @v8i1(<8 x i1> %m) { ; CHECK-LABEL: v8i1: ; CHECK: // %bb.0: ; CHECK-NEXT: shl v0.8b, v0.8b, #7 -; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, #0 -; CHECK-NEXT: brkb p1.b, p0/z, p1.b -; CHECK-NEXT: mov z0.b, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: index z1.b, #8, #-1 +; CHECK-NEXT: mov w9, #8 // =0x8 +; CHECK-NEXT: cmlt v0.8b, v0.8b, #0 +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: umaxv b0, v0.8b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: sub w8, w9, w8, uxtb +; CHECK-NEXT: whilelo p0.b, xzr, x8 +; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %x = call <8 x i1> @llvm.mask.beforefirst(<8 x i1> %m) @@ -73,10 +86,15 @@ define <4 x i1> @v4i1(<4 x i1> %m) { ; CHECK-LABEL: v4i1: ; CHECK: // %bb.0: ; CHECK-NEXT: shl v0.4h, v0.4h, #15 -; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: cmpne p1.h, p0/z, z0.h, #0 -; CHECK-NEXT: brkb p1.b, p0/z, p1.b -; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: index z1.h, #4, #-1 +; CHECK-NEXT: mov w9, #4 // =0x4 +; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: umaxv h0, v0.4h +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: sub w8, w9, w8, uxth +; CHECK-NEXT: whilelo p0.h, xzr, x8 +; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %x = call <4 x i1> @llvm.mask.beforefirst(<4 x i1> %m) @@ -87,10 +105,15 @@ define <2 x i1> @v2i1(<2 x i1> %m) { ; CHECK-LABEL: v2i1: ; CHECK: // %bb.0: ; CHECK-NEXT: shl v0.2s, v0.2s, #31 -; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0 -; CHECK-NEXT: brkb p1.b, p0/z, p1.b -; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: index z1.s, #2, #-1 +; CHECK-NEXT: mov w9, #2 // =0x2 +; CHECK-NEXT: cmlt v0.2s, v0.2s, #0 +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: sub w8, w9, w8 +; CHECK-NEXT: whilelo p0.s, xzr, x8 +; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %x = call <2 x i1> @llvm.mask.beforefirst(<2 x i1> %m) _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
