https://bugs.llvm.org/show_bug.cgi?id=41260
Bug ID: 41260
Summary: Scalar intrinsics like vqshrns_n_u32 generate
suboptimal vector instructions
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AArch64
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected],
[email protected], [email protected],
[email protected]
SISD intrinsics like vqshrns_n_u32 are currently codegen'd by clang to the
vector equivalent of the instruction, instead of the available scalar
instruction.
I think this is both a clang and LLVM issue as both need work to get this ISel
working, filing under backend for now.
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