| Issue |
90892
|
| Summary |
[RISC-V] Miscompile with rv64gcv_zvl256b
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
patrick-rivos
|
Testcase:
```c
unsigned int a;
int c = 1;
unsigned short d[200];
signed char e[400];
int k;
int main()
{
for (long h = 0; h < 20; ++h)
d[h] = 0x8000; // 16th bit is set
for (long i = 20; i < 40; ++i)
e[i] = 0;
for (short j = 0; j < 20; j += c)
{
k = -((int) d[j]);
k = ~k;
k = (unsigned short)(e[0] > k ? (signed char)(j * 20) : k);
a = a > k ? a : k;
}
__builtin_printf("%u\n", a);
return 0;
}
```
Commands:
```bash
> /scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang -march=rv64gcv_zvl256b -flto -O3 -fwrapv red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 red.out
65440
> /scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 red.out
32767
```
Reduced LLVM IR:
```llvm ir
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"
@d = global [200 x i16] zeroinitializer
@.str = constant [4 x i8] c"%u\0A\00"
define i32 @main() #0 {
entry:
store <16 x i16> <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>, ptr @d, align 32
%0 = load i16, ptr @d, align 8
%conv15.12 = zext i16 %0 to i32
%not.12 = or i32 %conv15.12, 0
%cmp17.not.12 = icmp sgt i32 %conv15.12, 0
%1 = and i32 %not.12, 0
%conv23.12 = select i1 %cmp17.not.12, i32 %1, i32 65520
%conv15.13 = zext i16 0 to i32
%not.13 = or i32 %conv15.13, 0
%cmp17.not.13 = icmp sgt i32 0, 0
%2 = and i32 %not.13, 0
%conv23.13 = select i1 %cmp17.not.13, i32 %2, i32 0
%cond29.12 = call i32 @llvm.umax.i32(i32 %conv23.12, i32 %conv23.13)
%conv15.14 = zext i16 0 to i32
%not.14 = or i32 %conv15.14, 0
%cmp17.not.14 = icmp sgt i32 0, 0
%3 = and i32 %not.14, 0
%conv23.14 = select i1 %cmp17.not.14, i32 %3, i32 0
%cond29.13 = call i32 @llvm.umax.i32(i32 %cond29.12, i32 %conv23.14)
%conv15.15 = zext i16 0 to i32
%not.15 = or i32 %conv15.15, 0
%cmp17.not.15 = icmp sgt i32 0, 0
%4 = and i32 %not.15, 0
%conv23.15 = select i1 %cmp17.not.15, i32 %4, i32 0
%cond29.14 = call i32 @llvm.umax.i32(i32 %cond29.13, i32 %conv23.15)
%cond29.19 = call i32 @llvm.umax.i32(i32 %cond29.14, i32 32767)
%call = tail call i32 (ptr, ...) @printf(ptr @.str, i32 %cond29.19)
ret i32 0
}
declare i32 @printf(ptr, ...)
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #1
; uselistorder directives
uselistorder ptr @llvm.umax.i32, { 3, 2, 1, 0 }
attributes #0 = { "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zaamo,-experimental-zabha,-experimental-zalasr,-experimental-zalrsc,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-h,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smepmp,-ssaia,-ssccptr,-sscofpmf,-sscounterenw,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
```
Commands:
```bash
/scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang -Xclang -disable-llvm-passes red.ll -o baseline.out
/scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/opt -passes=slp-vectorizer red.ll > opt.bc
/scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang -Xclang -disable-llvm-passes opt.bc -o opt.out
QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 baseline.out
65520
QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 opt.out
32767
```
`-Wl,-opt-bisect-limit` points to SLPVectorizer, but extracting the IR that passes before/fails after causes alive2 to flag it as UB.
https://alive2.llvm.org/ce/z/JyXU8-
The input c file passes sanitizers and does not appear to have any UB, so this might be a different pass misbehaving here before it gets to SLPVectorizer.
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