| Issue |
130217
|
| Summary |
[RISCV] Add assembler support for the Q extension
|
| Labels |
backend:RISC-V
|
| Assignees |
|
| Reporter |
topperc
|
I don't know of any hardware that implement this, but the opcodes are standardized and it is implemented in the binutils assembler. I think the cost of supporting in LLVM is relatively low and it could be a good first task for someone.
Thoughts @asb @jrtc27 @preames @lenary?
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