Issue 146015
Summary [MLIR][Affine] affine-pipeline-data-transfer-pass erases op attributes
Labels mlir
Assignees
Reporter sherylll
    version: 20.1.7

input:
```
// RUN: mlir-opt %s -affine-pipeline-data-transfer 
func.func @loop_nest_dma() {

  %A = memref.alloc() : memref<256 x f32, affine_map<(d0) -> (d0)>, 0>
  %Ah = memref.alloc() {alignment = 1024} : memref<32 x f32, affine_map<(d0) -> (d0)>, 1>

  %tag = memref.alloc() : memref<1 x f32>

  %zero = arith.constant 0 : index
  %num_elts = arith.constant 32 : index

  affine.for %i = 0 to 8 {
    affine.dma_start %A[%i], %Ah[%i], %tag[%zero], %num_elts : memref<256 x f32>, memref<32 x f32, 1>, memref<1 x f32>
    affine.dma_wait %tag[%zero], %num_elts : memref<1 x f32>
    %v = affine.load %Ah[%i] : memref<32 x f32, affine_map<(d0) -> (d0)>, 1>
  }
  memref.dealloc %tag : memref<1 x f32>
  memref.dealloc %Ah : memref<32 x f32, affine_map<(d0) -> (d0)>, 1>
 return
}
```
output:
```
#map = affine_map<(d0) -> (d0 - 1)>
#map1 = affine_map<(d0) -> (d0 mod 2)>
module {
  func.func @loop_nest_dma() {
 ...
    %alloc_1 = memref.alloc() : memref<2x32xf32, 1> // attributes get removed
    %alloc_2 = memref.alloc() : memref<2x1xf32>
 affine.dma_start %alloc[%c0], %alloc_1[%c0 mod 2, %c0], %alloc_2[%c0 mod 2, 0], %c32 : memref<256xf32>, memref<2x32xf32, 1>, memref<2x1xf32>
 affine.for %arg0 = 1 to 8 {
      affine.dma_start %alloc[%arg0], %alloc_1[%arg0 mod 2, %arg0], %alloc_2[%arg0 mod 2, 0], %c32 : memref<256xf32>, memref<2x32xf32, 1>, memref<2x1xf32>
      %4 = affine.apply #map(%arg0)
      %5 = affine.apply #map1(%4)
      %6 = affine.apply #map1(%4)
      affine.dma_wait %alloc_2[%4 mod 2, 0], %c32 : memref<2x1xf32>
      %7 = affine.load %alloc_1[%4 mod 2, %4] : memref<2x32xf32, 1>
    }
    ...
    return
  }
}
```

The alignment attribute is lost during this pass. Is this expected behavior? If not, adding an argument `cast<memref::AllocOp>(oldMemRef.getDefiningOp())->getAttrs()` to this line [this line](https://github.com/llvm/llvm-project/blob/main/mlir/lib/Dialect/Affine/Transforms/PipelineDataTransfer.cpp#L105) should fix the issue. 

_______________________________________________
llvm-bugs mailing list
llvm-bugs@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs

Reply via email to