| Issue |
148669
|
| Summary |
[AArch64] Expected a ZPR4StridedOrContiguous register, but got a ZPR4 register
|
| Labels |
backend:AArch64
|
| Assignees |
|
| Reporter |
sjoerdmeijer
|
For a build with expensive checks enabled, and this input:
```
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-unknown-linux-gnu"
define void @_Z4testytsybsxtyiyxttytiPtS_PA24_sPyS2_PxS2_PA23_tS2_PsPA23_aPiPaPA23_sPA23_SB_PA23_yPA23_S4_S2_SA_SA_PA23_SF_SG_SI_PA23_S7_(ptr %arr_5, ptr %arr_16, <vscale x 2 x i64> %0, <vscale x 2 x i1> %1, <vscale x 2 x i64> %vec.ind.next, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, <vscale x 2 x i16> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %vec.ind, <vscale x 2 x i64> %step.add, <vscale x 2 x i64> %6, <vscale x 2 x i64> %step.add.2, ptr %7, i1 %8, <vscale x 2 x i1> %9) #0 {
entry:
br label %vector.body1501
vector.body1501: ; preds = %vector.body1501, %entry
%vec.ind2 = phi <vscale x 2 x i64> [ zeroinitializer, %entry ], [ %vec.ind.next, %vector.body1501 ]
%vec.phi1503 = phi <vscale x 2 x i16> [ zeroinitializer, %entry ], [ %2, %vector.body1501 ]
%vec.phi1504 = phi <vscale x 2 x i16> [ zeroinitializer, %entry ], [ %3, %vector.body1501 ]
%vec.phi1505 = phi <vscale x 2 x i16> [ zeroinitializer, %entry ], [ %4, %vector.body1501 ]
%vec.phi1508 = phi <vscale x 2 x i64> [ zeroinitializer, %entry ], [ %34, %vector.body1501 ]
%vec.phi1509 = phi <vscale x 2 x i64> [ zeroinitializer, %entry ], [ %35, %vector.body1501 ]
%10 = or <vscale x 2 x i64> %vec.ind2, %step.add.2
tail call void @llvm.masked.scatter.nxv2i64.nxv2p0(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x ptr> zeroinitializer, i32 0, <vscale x 2 x i1> %1)
%11 = extractelement <vscale x 2 x i64> %10, i64 0
%12 = getelementptr i64, ptr %arr_5, i64 %11
%wide.vec1526 = load <vscale x 8 x i64>, ptr %12, align 8
%strided.vec1527 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64> %wide.vec1526)
%13 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %strided.vec1527, 0
%wide.vec1528 = load <vscale x 8 x i64>, ptr %7, align 8
%strided.vec1529 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64> %wide.vec1528)
%14 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %strided.vec1529, 0
%wide.vec1530 = load <vscale x 8 x i64>, ptr %arr_16, align 8
%strided.vec1531 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64> %wide.vec1530)
%15 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %strided.vec1531, 0
%wide.vec1532 = load <vscale x 8 x i64>, ptr %arr_5, align 8
%strided.vec1533 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64> %wide.vec1532)
%16 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %strided.vec1533, 0
%17 = icmp eq <vscale x 2 x i64> %13, zeroinitializer
%18 = icmp eq <vscale x 2 x i64> %14, zeroinitializer
%19 = icmp eq <vscale x 2 x i64> %15, zeroinitializer
%20 = icmp eq <vscale x 2 x i64> %16, zeroinitializer
%21 = and <vscale x 2 x i1> %1, %17
%22 = and <vscale x 2 x i1> %1, %18
%23 = and <vscale x 2 x i1> %1, %19
%24 = and <vscale x 2 x i1> %1, %20
%25 = zext <vscale x 2 x i1> %21 to <vscale x 2 x i16>
%26 = zext <vscale x 2 x i1> %22 to <vscale x 2 x i16>
%27 = zext <vscale x 2 x i1> %23 to <vscale x 2 x i16>
%28 = zext <vscale x 2 x i1> %24 to <vscale x 2 x i16>
%29 = xor <vscale x 2 x i16> %vec.phi1503, %25
%30 = xor <vscale x 2 x i16> %vec.phi1504, %26
%31 = xor <vscale x 2 x i16> %vec.phi1505, %27
%wide.vec1540 = load <vscale x 8 x i64>, ptr null, align 8
%strided.vec1541 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64> %wide.vec1540)
%32 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %strided.vec1541, 0
%33 = tail call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %32, <vscale x 2 x i64> %6)
%34 = xor <vscale x 2 x i64> %vec.phi1508, %33
%35 = xor <vscale x 2 x i64> %vec.phi1509, %0
br i1 %8, label %middle.block1547, label %vector.body1501
middle.block1547: ; preds = %vector.body1501
%bin.rdx1548 = xor <vscale x 2 x i16> %30, %29
%bin.rdx1549 = xor <vscale x 2 x i16> %31, %bin.rdx1548
%bin.rdx1550 = xor <vscale x 2 x i16> %28, %bin.rdx1549
%36 = tail call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %bin.rdx1550)
%bin.rdx1552 = xor <vscale x 2 x i64> %vec.phi1509, %vec.phi1508
store i16 %36, ptr %arr_5, align 2
ret void
; uselistorder directives
uselistorder <vscale x 2 x i1> %1, { 1, 2, 3, 4, 0 }
}
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
declare void @llvm.masked.scatter.nxv2i64.nxv2p0(<vscale x 2 x i64>, <vscale x 2 x ptr>, i32 immarg, <vscale x 2 x i1>) #2
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64>) #3
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16>) #1
; uselistorder directives
uselistorder ptr @llvm.vector.deinterleave4.nxv8i64, { 4, 3, 2, 1, 0 }
attributes #0 = { "target-cpu"="grace" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(none) }
```
We are running into this error:
```
*** Bad machine code: Illegal virtual register for instruction ***
- function: _Z4testytsybsxtyiyxttytiPtS_PA24_sPyS2_PxS2_PA23_tS2_PsPA23_aPiPaPA23_sPA23_SB_PA23_yPA23_S4_S2_SA_SA_PA23_SF_SG_SI_PA23_S7_
- basic block: %bb.1 vector.body1501 (0xaaaaaf6ccc00) [512B;1024B)
- instruction: 712B STR_ZZZZXI %72:zpr4, %stack.0, 0 :: (store (s512) into %stack.0, align 16)
- operand 0: %72:zpr4
Expected a ZPR4StridedOrContiguous register, but got a ZPR4 register
*** Bad machine code: Illegal virtual register for instruction ***
- function: _Z4testytsybsxtyiyxttytiPtS_PA24_sPyS2_PxS2_PA23_tS2_PsPA23_aPiPaPA23_sPA23_SB_PA23_yPA23_S4_S2_SA_SA_PA23_SF_SG_SI_PA23_S7_
- basic block: %bb.2 middle.block1547 (0xaaaaaf6ccfd0) [1024B;1392B)
- instruction: 1032B %73:zpr4 = LDR_ZZZZXI %stack.0, 0 :: (load (s512) from %stack.0, align 16)
- operand 0: %73:zpr4
Expected a ZPR4StridedOrContiguous register, but got a ZPR4 register
LLVM ERROR: Found 2 machine code errors.
```
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